Merge branch 'mlx5_realtime_ts' into rdma.git for-next
authorJason Gunthorpe <jgg@nvidia.com>
Tue, 22 Jun 2021 18:08:39 +0000 (15:08 -0300)
committerJason Gunthorpe <jgg@nvidia.com>
Tue, 22 Jun 2021 18:08:39 +0000 (15:08 -0300)
Aharon Landau says:

====================
In case device supports only real-time timestamp, the kernel will fail to
create QP despite rdma-core requested such timestamp type.

It is because device returns free-running timestamp, and the conversion
from free-running to real-time is performed in the user space.

This series fixes it, by returning real-time timestamp.
====================

* mlx5_realtime_ts:
  RDMA/mlx5: Support real-time timestamp directly from the device
  RDMA/mlx5: Refactor get_ts_format functions to simplify code

Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
1  2 
drivers/infiniband/hw/mlx5/cq.c
drivers/infiniband/hw/mlx5/main.c
drivers/infiniband/hw/mlx5/mlx5_ib.h
drivers/infiniband/hw/mlx5/qp.c
drivers/net/ethernet/mellanox/mlx5/core/en_main.c
include/uapi/rdma/mlx5-abi.h

Simple merge
index a536bdd6a9167f8390c4fb4634bf44adf5483ed6,a273cbb9369f853bcd3930dc2e3e74c613f0e3f7..46136b4b578dc0cbe61bf4f7e107b5dee90acba3
@@@ -1816,11 -1816,13 +1816,17 @@@ static int set_ucontext_resp(struct ib_
        if (MLX5_CAP_GEN(dev->mdev, ece_support))
                resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE;
  
+       if (rt_supported(MLX5_CAP_GEN(dev->mdev, sq_ts_format)) &&
+           rt_supported(MLX5_CAP_GEN(dev->mdev, rq_ts_format)) &&
+           rt_supported(MLX5_CAP_ROCE(dev->mdev, qp_ts_format)))
+               resp->comp_mask |=
+                       MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS;
        resp->num_dyn_bfregs = bfregi->num_dyn_bfregs;
 +
 +      if (MLX5_CAP_GEN(dev->mdev, drain_sigerr))
 +              resp->comp_mask |= MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS;
 +
        return 0;
  }
  
Simple merge
Simple merge
index 995faf8f44bd3fbdc8b6de3e7dad4dda1b15b5ea,82e3bc1eb57dfd2d8c18b234a3fda580716a3207..8597e6f22a1c77ac416fdeb9b257184210639b21
@@@ -101,7 -101,7 +101,8 @@@ enum mlx5_ib_alloc_ucontext_resp_mask 
        MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_CORE_CLOCK_OFFSET = 1UL << 0,
        MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_DUMP_FILL_MKEY    = 1UL << 1,
        MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_ECE               = 1UL << 2,
 +      MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_SQD2RTS           = 1UL << 3,
+       MLX5_IB_ALLOC_UCONTEXT_RESP_MASK_REAL_TIME_TS      = 1UL << 4,
  };
  
  enum mlx5_user_cmds_supp_uhw {