rtw89: configure mac port HIQ registers

HIQ is short for high queue that is used to send broadcast/multicast
packets right after TBTT in AP mode. Two registers, DTIM and window size,
are configured accordingly.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220107034239.22002-10-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c
index a7f5fba25511f298e28450d181016ebddf006896..0a006f3c3742d30bc41bba8b6acd26eb73c5b8fe 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/mac.c
+++ b/drivers/net/wireless/realtek/rtw89/mac.c
@@ -2876,6 +2876,36 @@ static void rtw89_mac_port_cfg_bcn_intv(struct rtw89_dev *rtwdev,
                                bcn_int);
 }
 
+static void rtw89_mac_port_cfg_hiq_win(struct rtw89_dev *rtwdev,
+                                      struct rtw89_vif *rtwvif)
+{
+       static const u32 hiq_win_addr[RTW89_PORT_NUM] = {
+               R_AX_P0MB_HGQ_WINDOW_CFG_0, R_AX_PORT_HGQ_WINDOW_CFG,
+               R_AX_PORT_HGQ_WINDOW_CFG + 1, R_AX_PORT_HGQ_WINDOW_CFG + 2,
+               R_AX_PORT_HGQ_WINDOW_CFG + 3,
+       };
+       u8 win = rtwvif->net_type == RTW89_NET_TYPE_AP_MODE ? 16 : 0;
+       u8 port = rtwvif->port;
+       u32 reg;
+
+       reg = rtw89_mac_reg_by_idx(hiq_win_addr[port], rtwvif->mac_idx);
+       rtw89_write8(rtwdev, reg, win);
+}
+
+static void rtw89_mac_port_cfg_hiq_dtim(struct rtw89_dev *rtwdev,
+                                       struct rtw89_vif *rtwvif)
+{
+       struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
+       const struct rtw89_port_reg *p = &rtw_port_base;
+       u32 addr;
+
+       addr = rtw89_mac_reg_by_idx(R_AX_MD_TSFT_STMP_CTL, rtwvif->mac_idx);
+       rtw89_write8_set(rtwdev, addr, B_AX_UPD_HGQMD | B_AX_UPD_TIMIE);
+
+       rtw89_write16_port_mask(rtwdev, rtwvif, p->dtim_ctrl, B_AX_DTIM_NUM_MASK,
+                               vif->bss_conf.dtim_period);
+}
+
 static void rtw89_mac_port_cfg_bcn_setup_time(struct rtw89_dev *rtwdev,
                                              struct rtw89_vif *rtwvif)
 {
@@ -3046,13 +3076,15 @@ int rtw89_mac_port_update(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
        rtw89_mac_port_cfg_rx_sync(rtwdev, rtwvif);
        rtw89_mac_port_cfg_tx_sw(rtwdev, rtwvif);
        rtw89_mac_port_cfg_bcn_intv(rtwdev, rtwvif);
+       rtw89_mac_port_cfg_hiq_win(rtwdev, rtwvif);
+       rtw89_mac_port_cfg_hiq_dtim(rtwdev, rtwvif);
+       rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif);
        rtw89_mac_port_cfg_bcn_setup_time(rtwdev, rtwvif);
        rtw89_mac_port_cfg_bcn_hold_time(rtwdev, rtwvif);
        rtw89_mac_port_cfg_bcn_mask_area(rtwdev, rtwvif);
        rtw89_mac_port_cfg_tbtt_early(rtwdev, rtwvif);
        rtw89_mac_port_cfg_bss_color(rtwdev, rtwvif);
        rtw89_mac_port_cfg_mbssid(rtwdev, rtwvif);
-       rtw89_mac_port_cfg_hiq_drop(rtwdev, rtwvif);
        rtw89_mac_port_cfg_func_en(rtwdev, rtwvif);
        fsleep(BCN_ERLY_SET_DLY);
        rtw89_mac_port_cfg_bcn_early(rtwdev, rtwvif);

diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index e0a416d37d0e89e8042461de978f6c6e709a97eb..5e5cb0fcfa8598c600d1160d135451e4f203dbfd 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -913,7 +913,7 @@
 #define R_AX_DTIM_CTRL_P2 0xC4A6
 #define R_AX_DTIM_CTRL_P3 0xC4E6
 #define R_AX_DTIM_CTRL_P4 0xC526
-#define B_AX_DTIM_NUM_MASK GENMASK(15, 0)
+#define B_AX_DTIM_NUM_MASK GENMASK(15, 8)
 #define B_AX_DTIM_CURRCNT_MASK GENMASK(7, 0)
 
 #define R_AX_TBTT_SHIFT_P0 0xC428
@@ -964,6 +964,11 @@
 #define B_AX_P0MB2_EN BIT(2)
 #define B_AX_P0MB1_EN BIT(1)
 
+#define R_AX_P0MB_HGQ_WINDOW_CFG_0 0xC590
+#define R_AX_P0MB_HGQ_WINDOW_CFG_0_C1 0xE590
+#define R_AX_PORT_HGQ_WINDOW_CFG 0xC5A0
+#define R_AX_PORT_HGQ_WINDOW_CFG_C1 0xE5A0
+
 #define R_AX_AMPDU_AGG_LIMIT 0xC610
 #define B_AX_AMPDU_MAX_TIME_MASK GENMASK(31, 24)
 #define B_AX_RA_TRY_RATE_AGG_LMT_MASK GENMASK(23, 16)
@@ -1080,6 +1085,13 @@
 #define B_AX_TCR_ZLD_USTIME_AFTERPHYTXON GENMASK(11, 8)
 #define B_AX_TCR_TXTIMEOUT GENMASK(7, 0)
 
+#define R_AX_MD_TSFT_STMP_CTL 0xCA08
+#define R_AX_MD_TSFT_STMP_CTL_C1 0xEA08
+#define B_AX_TSFT_OFS_MASK GENMASK(31, 16)
+#define B_AX_STMP_THSD_MASK GENMASK(15, 8)
+#define B_AX_UPD_HGQMD BIT(1)
+#define B_AX_UPD_TIMIE BIT(0)
+
 #define R_AX_PPWRBIT_SETTING 0xCA0C
 #define R_AX_PPWRBIT_SETTING_C1 0xEA0C