dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks

Add main gate clocks for controlling AUD and HSI CMUs:
  - gout_aud_cmu_aud_pclk
  - gout_hsi_cmu_hsi_pclk

While at it, add missing PPMU (Performance Profiling Monitor Unit)
clocks for CMU_HSI.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org>
Link: https://lore.kernel.org/r/20230223042133.26551-3-semen.protsenko@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h
index 8bb62e43fd608cac981398661a123ff6c36d7a7c..afacba338c9123b196c2f907f4f70d07abab9d3a 100644 (file)
--- a/include/dt-bindings/clock/exynos850.h
+++ b/include/dt-bindings/clock/exynos850.h
@@ -178,7 +178,8 @@
 #define IOCLK_AUDIOCDCLK5              58
 #define IOCLK_AUDIOCDCLK6              59
 #define TICK_USB                       60
-#define AUD_NR_CLK                     61
+#define CLK_GOUT_AUD_CMU_AUD_PCLK      61
+#define AUD_NR_CLK                     62
 
 /* CMU_CMGP */
 #define CLK_RCO_CMGP                   1
@@ -227,7 +228,10 @@
 #define CLK_GOUT_MMC_CARD_ACLK         11
 #define CLK_GOUT_MMC_CARD_SDCLKIN      12
 #define CLK_GOUT_SYSREG_HSI_PCLK       13
-#define HSI_NR_CLK                     14
+#define CLK_GOUT_HSI_PPMU_ACLK         14
+#define CLK_GOUT_HSI_PPMU_PCLK         15
+#define CLK_GOUT_HSI_CMU_HSI_PCLK      16
+#define HSI_NR_CLK                     17
 
 /* CMU_IS */
 #define CLK_MOUT_IS_BUS_USER           1