u32 pcgcctl;
        int ret = 0;
 
+       if (!hsotg->core_params->hibernation)
+               return -ENOTSUPP;
+
        pcgcctl = readl(hsotg->regs + PCGCTL);
        pcgcctl &= ~PCGCTL_STOPPCLK;
        writel(pcgcctl, hsotg->regs + PCGCTL);
        u32 pcgcctl;
        int ret = 0;
 
+       if (!hsotg->core_params->hibernation)
+               return -ENOTSUPP;
+
        /* Backup all registers */
        ret = dwc2_backup_global_registers(hsotg);
        if (ret) {
        hsotg->core_params->external_id_pin_ctl = val;
 }
 
+static void dwc2_set_param_hibernation(struct dwc2_hsotg *hsotg,
+               int val)
+{
+       if (DWC2_OUT_OF_BOUNDS(val, 0, 1)) {
+               if (val >= 0) {
+                       dev_err(hsotg->dev,
+                               "'%d' invalid for parameter hibernation\n",
+                               val);
+                       dev_err(hsotg->dev, "hibernation must be 0 or 1\n");
+               }
+               val = 0;
+               dev_dbg(hsotg->dev, "Setting hibernation to %d\n", val);
+       }
+
+       hsotg->core_params->hibernation = val;
+}
+
 /*
  * This function is called during module intialization to pass module parameters
  * for the DWC_otg core.
        dwc2_set_param_otg_ver(hsotg, params->otg_ver);
        dwc2_set_param_uframe_sched(hsotg, params->uframe_sched);
        dwc2_set_param_external_id_pin_ctl(hsotg, params->external_id_pin_ctl);
+       dwc2_set_param_hibernation(hsotg, params->hibernation);
 }
 
 /**
 
  *                      case.
  *                      0 - No (default)
  *                      1 - Yes
+ * @hibernation:       Specifies whether the controller support hibernation.
+ *                     If hibernation is enabled, the controller will enter
+ *                     hibernation in both peripheral and host mode when
+ *                     needed.
+ *                     0 - No (default)
+ *                     1 - Yes
  *
  * The following parameters may be specified when starting the module. These
  * parameters define how the DWC_otg controller should be configured. A
        int ahbcfg;
        int uframe_sched;
        int external_id_pin_ctl;
+       int hibernation;
 };
 
 /**
 
                        dctl &= ~DCTL_RMTWKUPSIG;
                        writel(dctl, hsotg->regs + DCTL);
                        ret = dwc2_exit_hibernation(hsotg, true);
-                       if (ret)
+                       if (ret && (ret != -ENOTSUPP))
                                dev_err(hsotg->dev, "exit hibernation failed\n");
 
                        call_gadget(hsotg, resume);
 
                        ret = dwc2_enter_hibernation(hsotg);
                        if (ret) {
-                               dev_err(hsotg->dev,
-                                       "enter hibernation failed\n");
+                               if (ret != -ENOTSUPP)
+                                       dev_err(hsotg->dev,
+                                                       "enter hibernation failed\n");
                                goto skip_power_saving;
                        }
 
 
        .ahbcfg                         = 0x10,
        .uframe_sched                   = 0,
        .external_id_pin_ctl            = -1,
+       .hibernation                    = -1,
 };
 
 static const struct dwc2_core_params params_rk3066 = {
        .ahbcfg                         = 0x7, /* INCR16 */
        .uframe_sched                   = -1,
        .external_id_pin_ctl            = -1,
+       .hibernation                    = -1,
 };
 
 /**