perf/x86/intel/pt: Add a capability and config bit for event tracing

As of Intel SDM (https://www.intel.com/sdm) version 076, there is a new
Intel PT feature called Event Trace which is enabled config bit 31.

Event Trace exposes details about asynchronous events such as interrupts
and VM-Entry/Exit.

Add a capability and config bit for Event Trace.

Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Signed-off-by: Adrian Hunter <adrian.hunter@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Adrian Hunter <adrian.hunter@intel.com>
Link: https://lore.kernel.org/r/20220126104815.2807416-2-adrian.hunter@intel.com

diff --git a/arch/x86/events/intel/pt.c b/arch/x86/events/intel/pt.c
index f061dc2bd5f091beea2e5de0b54b4a6bdc9529f8..f339c88d17f91fd290dae611274289e4096a5e3f 100644 (file)
--- a/arch/x86/events/intel/pt.c
+++ b/arch/x86/events/intel/pt.c
@@ -59,6 +59,7 @@ static struct pt_cap_desc {
        PT_CAP(mtc,                     0, CPUID_EBX, BIT(3)),
        PT_CAP(ptwrite,                 0, CPUID_EBX, BIT(4)),
        PT_CAP(power_event_trace,       0, CPUID_EBX, BIT(5)),
+       PT_CAP(event_trace,             0, CPUID_EBX, BIT(7)),
        PT_CAP(topa_output,             0, CPUID_ECX, BIT(0)),
        PT_CAP(topa_multiple_entries,   0, CPUID_ECX, BIT(1)),
        PT_CAP(single_range_output,     0, CPUID_ECX, BIT(2)),
@@ -110,6 +111,7 @@ PMU_FORMAT_ATTR(tsc,                "config:10"     );
 PMU_FORMAT_ATTR(noretcomp,     "config:11"     );
 PMU_FORMAT_ATTR(ptw,           "config:12"     );
 PMU_FORMAT_ATTR(branch,                "config:13"     );
+PMU_FORMAT_ATTR(event,         "config:31"     );
 PMU_FORMAT_ATTR(mtc_period,    "config:14-17"  );
 PMU_FORMAT_ATTR(cyc_thresh,    "config:19-22"  );
 PMU_FORMAT_ATTR(psb_period,    "config:24-27"  );
@@ -118,6 +120,7 @@ static struct attribute *pt_formats_attr[] = {
        &format_attr_pt.attr,
        &format_attr_cyc.attr,
        &format_attr_pwr_evt.attr,
+       &format_attr_event.attr,
        &format_attr_fup_on_ptw.attr,
        &format_attr_mtc.attr,
        &format_attr_tsc.attr,
@@ -298,6 +301,7 @@ fail:
                        RTIT_CTL_CYC_PSB        | \
                        RTIT_CTL_MTC            | \
                        RTIT_CTL_PWR_EVT_EN     | \
+                       RTIT_CTL_EVENT_EN       | \
                        RTIT_CTL_FUP_ON_PTW     | \
                        RTIT_CTL_PTW_EN)
 
@@ -352,6 +356,10 @@ static bool pt_event_valid(struct perf_event *event)
            !intel_pt_validate_hw_cap(PT_CAP_power_event_trace))
                return false;
 
+       if (config & RTIT_CTL_EVENT_EN &&
+           !intel_pt_validate_hw_cap(PT_CAP_event_trace))
+               return false;
+
        if (config & RTIT_CTL_PTW) {
                if (!intel_pt_validate_hw_cap(PT_CAP_ptwrite))
                        return false;

diff --git a/arch/x86/include/asm/intel_pt.h b/arch/x86/include/asm/intel_pt.h
index ebe8d2ea44fe0973076f369273bf94394fcabf09..d1ef9cb5884748f73cec583ba1b895192f124315 100644 (file)
--- a/arch/x86/include/asm/intel_pt.h
+++ b/arch/x86/include/asm/intel_pt.h
@@ -13,6 +13,7 @@ enum pt_capabilities {
        PT_CAP_mtc,
        PT_CAP_ptwrite,
        PT_CAP_power_event_trace,
+       PT_CAP_event_trace,
        PT_CAP_topa_output,
        PT_CAP_topa_multiple_entries,
        PT_CAP_single_range_output,

diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 3faf0f97edb1bcd3ebdb2d9d93535b091f8136bf..79b392d893e31cfcc3bdac676ad66dbeaf12b609 100644 (file)
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -205,6 +205,7 @@
 #define RTIT_CTL_DISRETC               BIT(11)
 #define RTIT_CTL_PTW_EN                        BIT(12)
 #define RTIT_CTL_BRANCH_EN             BIT(13)
+#define RTIT_CTL_EVENT_EN              BIT(31)
 #define RTIT_CTL_MTC_RANGE_OFFSET      14
 #define RTIT_CTL_MTC_RANGE             (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
 #define RTIT_CTL_CYC_THRESH_OFFSET     19