drm/i915: Consolidate condition for Wa_22011802037

The workaround bounds for Wa_22011802037 are somewhat complex and are
replicated in several places throughout the code.  Pull the condition
out to a helper function to prevent mistakes if this condition needs to
change again in the future.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230821180619.650007-12-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index ee15486fed0daa57479b07da01e2b7c3ea78391b..dfb69fc977a063feba4e632c48056b23f1799c55 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -1617,9 +1617,7 @@ static int __intel_engine_stop_cs(struct intel_engine_cs *engine,
         * Wa_22011802037: Prior to doing a reset, ensure CS is
         * stopped, set ring stop bit and prefetch disable bit to halt CS
         */
-       if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
-           (GRAPHICS_VER(engine->i915) >= 11 &&
-           GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
+       if (intel_engine_reset_needs_wa_22011802037(engine->gt))
                intel_uncore_write_fw(uncore, RING_MODE_GEN7(engine->mmio_base),
                                      _MASKED_BIT_ENABLE(GEN12_GFX_PREFETCH_DISABLE));
 

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 8a641bcf777cb4da2c211911a470272d759314a4..4d05321dc5b5ecbbdb183355d41a50b3a62b9fd0 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3001,9 +3001,7 @@ static void execlists_reset_prepare(struct intel_engine_cs *engine)
         * Wa_22011802037: In addition to stopping the cs, we need
         * to wait for any pending mi force wakeups
         */
-       if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
-           (GRAPHICS_VER(engine->i915) >= 11 &&
-           GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70)))
+       if (intel_engine_reset_needs_wa_22011802037(engine->gt))
                intel_engine_wait_for_pending_mi_fw(engine);
 
        engine->execlists.reset_ccid = active_ccid(engine);

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index cc6bd21a3e51f184234af52b629f465457e98a77..1ff7b42521c90053e28f5a80f8c5e9fb204157bc 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -1632,6 +1632,24 @@ void __intel_fini_wedge(struct intel_wedge_me *w)
        w->gt = NULL;
 }
 
+/*
+ * Wa_22011802037 requires that we (or the GuC) ensure that no command
+ * streamers are executing MI_FORCE_WAKE while an engine reset is initiated.
+ */
+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt)
+{
+       if (GRAPHICS_VER(gt->i915) < 11)
+               return false;
+
+       if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0))
+               return true;
+
+       if (GRAPHICS_VER_FULL(gt->i915) >= IP_VER(12, 70))
+               return false;
+
+       return true;
+}
+
 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 #include "selftest_reset.c"
 #include "selftest_hangcheck.c"

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.h b/drivers/gpu/drm/i915/gt/intel_reset.h
index 25c975b6e8fc01db398cba1dc09f9bb12b3a86bd..f615b30b81c59424cda4c98143703e9a3a5a769d 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_reset.h
+++ b/drivers/gpu/drm/i915/gt/intel_reset.h
@@ -78,4 +78,6 @@ void __intel_fini_wedge(struct intel_wedge_me *w);
 bool intel_has_gpu_reset(const struct intel_gt *gt);
 bool intel_has_reset_engine(const struct intel_gt *gt);
 
+bool intel_engine_reset_needs_wa_22011802037(struct intel_gt *gt);
+
 #endif /* I915_RESET_H */

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
index 82a2ecc12b212833dfe73077592889b2566290b4..da967938fea5841cc976a334765a9c6304003da1 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc.c
@@ -288,9 +288,7 @@ static u32 guc_ctl_wa_flags(struct intel_guc *guc)
                flags |= GUC_WA_DUAL_QUEUE;
 
        /* Wa_22011802037: graphics version 11/12 */
-       if (IS_MTL_GRAPHICS_STEP(gt->i915, M, STEP_A0, STEP_B0) ||
-           (GRAPHICS_VER(gt->i915) >= 11 &&
-           GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70)))
+       if (intel_engine_reset_needs_wa_22011802037(gt))
                flags |= GUC_WA_PRE_PARSER;
 
        /*

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index a0e3ef1c65d246b80696a5503b7c284b0e205b44..1bd5d8f7c40b352f5e0bca686c908372a68ee2d6 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -1658,9 +1658,7 @@ static void guc_engine_reset_prepare(struct intel_engine_cs *engine)
         * Wa_22011802037: In addition to stopping the cs, we need
         * to wait for any pending mi force wakeups
         */
-       if (IS_MTL_GRAPHICS_STEP(engine->i915, M, STEP_A0, STEP_B0) ||
-           (GRAPHICS_VER(engine->i915) >= 11 &&
-            GRAPHICS_VER_FULL(engine->i915) < IP_VER(12, 70))) {
+       if (intel_engine_reset_needs_wa_22011802037(engine->gt)) {
                intel_engine_stop_cs(engine);
                intel_engine_wait_for_pending_mi_fw(engine);
        }