ARM: dts: add DT for lan966 SoC and 2-port board pcb8291

This patch adds basic DT for Microchip lan966x SoC and associated board
pcb8291(2-port EVB). Adds peripherals required to allow booting: Interrupt
Controller, Clock, Generic ARMv7 Timers, Synopsys Timer, Flexcoms, GPIOs.
Also adds other peripherals like crypto(AES/SHA), DMA, Watchdog Timer, TRNG
and MCAN0.

Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
Reviewed-by: Michael Walle <michael@walle.cc>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20220221080858.14233-1-kavyasree.kotagiri@microchip.com

diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 235ad559acb2869481615b78abe4e933630bfbb0..c17a7308ff442bf8439f585970544f302590235e 100644 (file)
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -735,6 +735,8 @@ dtb-$(CONFIG_SOC_IMX7D) += \
 dtb-$(CONFIG_SOC_IMX7ULP) += \
        imx7ulp-com.dtb \
        imx7ulp-evk.dtb
+dtb-$(CONFIG_SOC_LAN966) += \
+       lan966x-pcb8291.dtb
 dtb-$(CONFIG_SOC_LS1021A) += \
        ls1021a-moxa-uc-8410a.dtb \
        ls1021a-qds.dtb \

diff --git a/arch/arm/boot/dts/lan966x-pcb8291.dts b/arch/arm/boot/dts/lan966x-pcb8291.dts
new file mode 100644 (file)
index 0000000..3281af9
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x-pcb8291.dts
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * lan966x_pcb8291.dts - Device Tree file for PCB8291
+ */
+/dts-v1/;
+#include "lan966x.dtsi"
+
+/ {
+       model = "Microchip EVB - LAN9662";
+       compatible = "microchip,lan9662-pcb8291", "microchip,lan9662", "microchip,lan966";
+
+       chosen {
+               stdout-path = "serial0:115200n8";
+       };
+
+       aliases {
+               serial0 = &usart3;
+       };
+};
+
+&gpio {
+       fc_shrd7_pins: fc_shrd7-pins {
+               pins = "GPIO_49";
+               function = "fc_shrd7";
+       };
+
+       fc_shrd8_pins: fc_shrd8-pins {
+               pins = "GPIO_54";
+               function = "fc_shrd8";
+       };
+
+       fc3_b_pins: fcb3-spi-pins {
+               /* SCK, RXD, TXD */
+               pins = "GPIO_51", "GPIO_52", "GPIO_53";
+               function = "fc3_b";
+       };
+
+       can0_b_pins:  can0_b_pins {
+               /* RX, TX */
+               pins = "GPIO_35", "GPIO_36";
+               function = "can0_b";
+       };
+};
+
+&can0 {
+       pinctrl-0 = <&can0_b_pins>;
+       pinctrl-names = "default";
+       status = "okay";
+};
+
+&flx3 {
+       atmel,flexcom-mode = <ATMEL_FLEXCOM_MODE_USART>;
+       status = "okay";
+
+       usart3: serial@200 {
+               pinctrl-0 = <&fc3_b_pins>, <&fc_shrd7_pins>, <&fc_shrd8_pins>;
+               pinctrl-names = "default";
+               status = "okay";
+       };
+};
+
+&watchdog {
+       status = "okay";
+};

diff --git a/arch/arm/boot/dts/lan966x.dtsi b/arch/arm/boot/dts/lan966x.dtsi
new file mode 100644 (file)
index 0000000..7d28696
--- /dev/null
+++ b/arch/arm/boot/dts/lan966x.dtsi
@@ -0,0 +1,237 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * lan966x.dtsi - Device Tree Include file for Microchip LAN966 family SoC
+ *
+ * Copyright (C) 2021 Microchip Technology, Inc. and its subsidiaries
+ *
+ * Author: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com>
+ *
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/mfd/atmel-flexcom.h>
+#include <dt-bindings/dma/at91.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/clock/microchip,lan966x.h>
+
+/ {
+       model = "Microchip LAN966 family SoC";
+       compatible = "microchip,lan966";
+       interrupt-parent = <&gic>;
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       cpus {
+               #address-cells = <1>;
+               #size-cells = <0>;
+
+               cpu@0 {
+                       device_type = "cpu";
+                       compatible = "arm,cortex-a7";
+                       clock-frequency = <600000000>;
+                       reg = <0x0>;
+               };
+       };
+
+       clocks {
+               sys_clk: sys_clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <162500000>;
+               };
+
+               cpu_clk: cpu_clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <600000000>;
+               };
+
+               ddr_clk: ddr_clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <300000000>;
+               };
+
+               nic_clk: nic_clk {
+                       compatible = "fixed-clock";
+                       #clock-cells = <0>;
+                       clock-frequency = <200000000>;
+               };
+       };
+
+       clks: clock-controller@e00c00a8 {
+               compatible = "microchip,lan966x-gck";
+               #clock-cells = <1>;
+               clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
+               clock-names = "cpu", "ddr", "sys";
+               reg = <0xe00c00a8 0x38>;
+       };
+
+       timer {
+               compatible = "arm,armv7-timer";
+               interrupt-parent = <&gic>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
+               clock-frequency = <37500000>;
+       };
+
+       soc {
+               compatible = "simple-bus";
+               #address-cells = <1>;
+               #size-cells = <1>;
+               ranges;
+
+               flx0: flexcom@e0040000 {
+                       compatible = "atmel,sama5d2-flexcom";
+                       reg = <0xe0040000 0x100>;
+                       clocks = <&clks GCK_ID_FLEXCOM0>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0xe0040000 0x800>;
+                       status = "disabled";
+               };
+
+               flx1: flexcom@e0044000 {
+                       compatible = "atmel,sama5d2-flexcom";
+                       reg = <0xe0044000 0x100>;
+                       clocks = <&clks GCK_ID_FLEXCOM1>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0xe0044000 0x800>;
+                       status = "disabled";
+               };
+
+               trng: rng@e0048000 {
+                       compatible = "atmel,at91sam9g45-trng";
+                       reg = <0xe0048000 0x100>;
+                       clocks = <&nic_clk>;
+               };
+
+               aes: crypto@e004c000 {
+                       compatible = "atmel,at91sam9g46-aes";
+                       reg = <0xe004c000 0x100>;
+                       interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
+                       dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
+                              <&dma0 AT91_XDMAC_DT_PERID(12)>;
+                       dma-names = "rx", "tx";
+                       clocks = <&nic_clk>;
+                       clock-names = "aes_clk";
+               };
+
+               flx2: flexcom@e0060000 {
+                       compatible = "atmel,sama5d2-flexcom";
+                       reg = <0xe0060000 0x100>;
+                       clocks = <&clks GCK_ID_FLEXCOM2>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0xe0060000 0x800>;
+                       status = "disabled";
+               };
+
+               flx3: flexcom@e0064000 {
+                       compatible = "atmel,sama5d2-flexcom";
+                       reg = <0xe0064000 0x100>;
+                       clocks = <&clks GCK_ID_FLEXCOM3>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0xe0064000 0x800>;
+                       status = "disabled";
+
+                       usart3: serial@200 {
+                               compatible = "atmel,at91sam9260-usart";
+                               reg = <0x200 0x200>;
+                               interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
+                               clocks = <&nic_clk>;
+                               clock-names = "usart";
+                               atmel,fifo-size = <32>;
+                               status = "disabled";
+                       };
+               };
+
+               dma0: dma-controller@e0068000 {
+                       compatible = "microchip,sama7g5-dma";
+                       reg = <0xe0068000 0x1000>;
+                       interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+                       #dma-cells = <1>;
+                       clocks = <&nic_clk>;
+                       clock-names = "dma_clk";
+               };
+
+               sha: crypto@e006c000 {
+                       compatible = "atmel,at91sam9g46-sha";
+                       reg = <0xe006c000 0xec>;
+                       interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
+                       dmas = <&dma0 AT91_XDMAC_DT_PERID(14)>;
+                       dma-names = "tx";
+                       clocks = <&nic_clk>;
+                       clock-names = "sha_clk";
+               };
+
+               flx4: flexcom@e0070000 {
+                       compatible = "atmel,sama5d2-flexcom";
+                       reg = <0xe0070000 0x100>;
+                       clocks = <&clks GCK_ID_FLEXCOM4>;
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0xe0070000 0x800>;
+                       status = "disabled";
+               };
+
+               timer0: timer@e008c000 {
+                       compatible = "snps,dw-apb-timer";
+                       reg = <0xe008c000 0x400>;
+                       clocks = <&nic_clk>;
+                       clock-names = "timer";
+                       interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
+               watchdog: watchdog@e0090000 {
+                       compatible = "snps,dw-wdt";
+                       reg = <0xe0090000 0x1000>;
+                       interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&nic_clk>;
+                       status = "disabled";
+               };
+
+               can0: can@e081c000 {
+                       compatible = "bosch,m_can";
+                       reg = <0xe081c000 0xfc>, <0x00100000 0x4000>;
+                       reg-names = "m_can", "message_ram";
+                       interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-names = "int0", "int1";
+                       clocks = <&clks GCK_ID_MCAN0>, <&clks GCK_ID_MCAN0>;
+                       clock-names = "hclk", "cclk";
+                       assigned-clocks = <&clks GCK_ID_MCAN0>;
+                       assigned-clock-rates = <40000000>;
+                       bosch,mram-cfg = <0x0 0 0 64 0 0 32 32>;
+                       status = "disabled";
+               };
+
+               gpio: pinctrl@e2004064 {
+                       compatible = "microchip,lan966x-pinctrl";
+                       reg = <0xe2004064 0xb4>,
+                           <0xe2010024 0x138>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       gpio-ranges = <&gpio 0 0 78>;
+                       interrupt-controller;
+                       interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+                       #interrupt-cells = <2>;
+               };
+
+               gic: interrupt-controller@e8c11000 {
+                       compatible = "arm,gic-400", "arm,cortex-a7-gic";
+                       #interrupt-cells = <3>;
+                       interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       reg = <0xe8c11000 0x1000>,
+                             <0xe8c12000 0x2000>,
+                             <0xe8c14000 0x2000>,
+                             <0xe8c16000 0x2000>;
+               };
+       };
+};