drm/amd/smu: Increace dpm level count only for smu v13.0.2

Only V13.0.2 on SMU v13 will get 0 based max level from fw and
increment by one, other ASIC will not need for this.
V2: replace the asic_type check with ip versioning check.

Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index cf09e30bdfe0bcf61067fa7934fe337b704cfe6e..e0514ce3ee5738ebc188b6daed68725d69e92b06 100644 (file)
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -1750,8 +1750,8 @@ int smu_v13_0_get_dpm_level_count(struct smu_context *smu,
        int ret;
 
        ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, value);
-       /* FW returns 0 based max level, increment by one */
-       if (!ret && value)
+       /* SMU v13.0.2 FW returns 0 based max level, increment by one for it */
+       if((smu->adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 2)) && (!ret && value))
                ++(*value);
 
        return ret;