arm64: dts: rockchip: add Quartz64-A con40 hardware

The Quartz64-A has a 40 pin connector that exposes various functions.
Annotate the functions exposed in the device tree.
Enable i2c3, which is pulled up to vcc_3v3 on board.

The following functions are currently exposed:
i2c3
spi1
uart2
uart0
spdif

Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Link: https://lore.kernel.org/r/20220128003809.3291407-5-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
index 94a164d6bce948bd4535ce6442013d1a43a2b55d..8332627f483b1d2e32281852aa474db1b828d1f0 100644 (file)
--- a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-a.dts
@@ -467,6 +467,14 @@
        };
 };
 
+/* i2c3 is exposed on con40
+ * pin 3 - i2c3_sda_m0, pullup to vcc_3v3
+ * pin 5 - i2c3_scl_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+       status = "okay";
+};
+
 &i2s1_8ch {
        pinctrl-names = "default";
        pinctrl-0 = <&i2s1m0_sclktx
@@ -583,10 +591,17 @@
        status = "okay";
 };
 
+/* spdif is exposed on con40 pin 18 */
 &spdif {
        status = "okay";
 };
 
+/* spi1 is exposed on con40
+ * pin 11 - spi1_mosi_m1
+ * pin 13 - spi1_miso_m1
+ * pin 15 - spi1_clk_m1
+ * pin 17 - spi1_cs0_m1
+ */
 &spi1 {
        pinctrl-names = "default";
        pinctrl-0 = <&spi1m1_cs0 &spi1m1_pins>;
@@ -600,6 +615,10 @@
        status = "okay";
 };
 
+/* uart0 is exposed on con40
+ * pin 12 - uart0_tx
+ * pin 14 - uart0_rx
+ */
 &uart0 {
        pinctrl-names = "default";
        pinctrl-0 = <&uart0_xfer>;
@@ -626,6 +645,10 @@
        };
 };
 
+/* uart2 is exposed on con40
+ * pin 8 - uart2_tx_m0_debug
+ * pin 10 - uart2_rx_m0_debug
+ */
 &uart2 {
        status = "okay";
 };