drm/xe: base definitions for the GSCCS

The first step in introducing the GSCCS is to add all the basic defs for
it (name, mmio base, class/instance, lrc size etc).

Bspec: 60149, 60421, 63752
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230817201831.1583172-3-daniele.ceraolospurio@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 1179bbd16a97b9aee76118b24c4fb4acde755537..5f635682ce5adc213fadd38c282b3f4449c9d4df 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -376,6 +376,7 @@
 #define   INTR_ENGINE_CLASS(x)                 REG_FIELD_GET(GENMASK(18, 16), x)
 #define   INTR_ENGINE_INTR(x)                  REG_FIELD_GET(GENMASK(15, 0), x)
 #define   OTHER_GUC_INSTANCE                   0
+#define   OTHER_GSC_INSTANCE                   6
 
 #define RENDER_COPY_INTR_ENABLE                        XE_REG(0x190030)
 #define VCS_VECS_INTR_ENABLE                   XE_REG(0x190034)

diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
index 25275a36b2808ccc1bb90491736100688d906086..be496a3946d83424b58ce84fc4eafcdc7179bd32 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_regs.h
@@ -33,6 +33,7 @@
 #define XEHPC_BCS6_RING_BASE                   0x3ea000
 #define XEHPC_BCS7_RING_BASE                   0x3ec000
 #define XEHPC_BCS8_RING_BASE                   0x3ee000
+#define GSCCS_RING_BASE                                0x11a000
 #define   GT_WAIT_SEMAPHORE_INTERRUPT          REG_BIT(11)
 #define   GT_CONTEXT_SWITCH_INTERRUPT          REG_BIT(8)
 #define   GT_RENDER_PIPECTL_NOTIFY_INTERRUPT   REG_BIT(4)

diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c
index c2adff770614270763ed64ef7ad01f581e52e546..f6619688f92fd311afed52c7e1862735c42f2952 100644 (file)
--- a/drivers/gpu/drm/xe/xe_exec_queue.c
+++ b/drivers/gpu/drm/xe/xe_exec_queue.c
@@ -195,6 +195,9 @@ void xe_exec_queue_assign_name(struct xe_exec_queue *q, u32 instance)
        case XE_ENGINE_CLASS_COMPUTE:
                sprintf(q->name, "ccs%d", instance);
                break;
+       case XE_ENGINE_CLASS_OTHER:
+               sprintf(q->name, "gsccs%d", instance);
+               break;
        default:
                XE_WARN_ON(q->class);
        }

diff --git a/drivers/gpu/drm/xe/xe_guc.h b/drivers/gpu/drm/xe/xe_guc.h
index f64f22e971697acda4c9f8d2c455b0de11285356..3addd8fc674afac00b92257ac39f25b08279f76e 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc.h
+++ b/drivers/gpu/drm/xe/xe_guc.h
@@ -51,6 +51,7 @@ static inline u16 xe_engine_class_to_guc_class(enum xe_engine_class class)
        case XE_ENGINE_CLASS_COMPUTE:
                return GUC_COMPUTE_CLASS;
        case XE_ENGINE_CLASS_OTHER:
+               return GUC_GSC_OTHER_CLASS;
        default:
                XE_WARN_ON(class);
                return -1;

diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
index 7d1244df959df05ff65ab25cb080d9e6c232709c..5edee24b97c96f3590c00842ebeaf2bb23b661b7 100644 (file)
--- a/drivers/gpu/drm/xe/xe_guc_ads.c
+++ b/drivers/gpu/drm/xe/xe_guc_ads.c
@@ -253,9 +253,6 @@ static size_t calculate_golden_lrc_size(struct xe_guc_ads *ads)
        int class;
 
        for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
-               if (class == XE_ENGINE_CLASS_OTHER)
-                       continue;
-
                if (!engine_enable_mask(gt, class))
                        continue;
 
@@ -350,6 +347,8 @@ static void fill_engine_enable_masks(struct xe_gt *gt,
                       engine_enable_mask(gt, XE_ENGINE_CLASS_VIDEO_ENHANCE));
        info_map_write(xe, info_map, engine_enabled_masks[GUC_COMPUTE_CLASS],
                       engine_enable_mask(gt, XE_ENGINE_CLASS_COMPUTE));
+       info_map_write(xe, info_map, engine_enabled_masks[GUC_GSC_OTHER_CLASS],
+                      engine_enable_mask(gt, XE_ENGINE_CLASS_OTHER));
 }
 
 static void guc_prep_golden_lrc_null(struct xe_guc_ads *ads)
@@ -638,9 +637,6 @@ static void guc_populate_golden_lrc(struct xe_guc_ads *ads)
        for (class = 0; class < XE_ENGINE_CLASS_MAX; ++class) {
                u8 guc_class;
 
-               if (class == XE_ENGINE_CLASS_OTHER)
-                       continue;
-
                guc_class = xe_engine_class_to_guc_class(class);
 
                if (!info_map_read(xe, &info_map,

diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
index 4c812d04e182395da0919b43ece38e548118bdb3..32a5bd9d8e6b690dd7b75c18cc73381ec2146fc5 100644 (file)
--- a/drivers/gpu/drm/xe/xe_hw_engine.c
+++ b/drivers/gpu/drm/xe/xe_hw_engine.c
@@ -219,6 +219,13 @@ static const struct engine_info engine_infos[] = {
                .domain = XE_FW_RENDER,
                .mmio_base = COMPUTE3_RING_BASE,
        },
+       [XE_HW_ENGINE_GSCCS0] = {
+               .name = "gsccs0",
+               .class = XE_ENGINE_CLASS_OTHER,
+               .instance = OTHER_GSC_INSTANCE,
+               .domain = XE_FW_GSC,
+               .mmio_base = GSCCS_RING_BASE,
+       },
 };
 
 static void hw_engine_fini(struct drm_device *drm, void *arg)

diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h
index 97d9ba31b5fc7611d3ca862323d682a203e7d3ac..cd4bc1412a3ff7f699c5c79e1aef649387b20fe7 100644 (file)
--- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
+++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
@@ -53,6 +53,8 @@ enum xe_hw_engine_id {
        XE_HW_ENGINE_CCS2,
        XE_HW_ENGINE_CCS3,
 #define XE_HW_ENGINE_CCS_MASK  GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
+       XE_HW_ENGINE_GSCCS0,
+#define XE_HW_ENGINE_GSCCS_MASK        GENMASK_ULL(XE_HW_ENGINE_GSCCS0, XE_HW_ENGINE_GSCCS0)
        XE_NUM_HW_ENGINES,
 };
 

diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
index 09db8da261a399d9a6aabf5503f39884a9fc09ef..7a7fdcdadf372a182fa738e5e0f5fbee8459319f 100644 (file)
--- a/drivers/gpu/drm/xe/xe_lrc.c
+++ b/drivers/gpu/drm/xe/xe_lrc.c
@@ -46,6 +46,7 @@ size_t xe_lrc_size(struct xe_device *xe, enum xe_engine_class class)
        case XE_ENGINE_CLASS_COPY:
        case XE_ENGINE_CLASS_VIDEO_DECODE:
        case XE_ENGINE_CLASS_VIDEO_ENHANCE:
+       case XE_ENGINE_CLASS_OTHER:
                return 2 * SZ_4K;
        }
 }