net/mlx5: Remove not-implemented IPsec capabilities
authorLeon Romanovsky <leonro@nvidia.com>
Wed, 6 Apr 2022 08:25:52 +0000 (11:25 +0300)
committerLeon Romanovsky <leonro@nvidia.com>
Sat, 9 Apr 2022 05:25:07 +0000 (08:25 +0300)
Clean a capabilities enum to remove not-implemented bits.

Link: https://lore.kernel.org/r/1044bb7b779107ff38e48e3f6553421104f3f819.1649232994.git.leonro@nvidia.com
Reviewed-by: Raed Salem <raeds@nvidia.com>
Signed-off-by: Leon Romanovsky <leonro@nvidia.com>
drivers/net/ethernet/mellanox/mlx5/core/en_accel/ipsec_offload.c
include/linux/mlx5/accel.h

index f0f44bd95cc97dbf0ba5bfbb25fbf8cdd877582f..37c9880719cf6872535c28822ea178d7a19edafd 100644 (file)
@@ -51,10 +51,8 @@ u32 mlx5_ipsec_device_caps(struct mlx5_core_dev *mdev)
            MLX5_CAP_IPSEC(mdev, ipsec_crypto_esp_aes_gcm_128_decrypt))
                caps |= MLX5_ACCEL_IPSEC_CAP_ESP;
 
-       if (MLX5_CAP_IPSEC(mdev, ipsec_esn)) {
+       if (MLX5_CAP_IPSEC(mdev, ipsec_esn))
                caps |= MLX5_ACCEL_IPSEC_CAP_ESN;
-               caps |= MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN;
-       }
 
        /* We can accommodate up to 2^24 different IPsec objects
         * because we use up to 24 bit in flow table metadata
index 73e4d50a9f0244a23d868473a39fc908e352eea7..0f2596297f6a3f3ba3e45942ccd59f35207f6e5a 100644 (file)
@@ -113,13 +113,10 @@ struct mlx5_accel_esp_xfrm {
 
 enum mlx5_accel_ipsec_cap {
        MLX5_ACCEL_IPSEC_CAP_DEVICE             = 1 << 0,
-       MLX5_ACCEL_IPSEC_CAP_REQUIRED_METADATA  = 1 << 1,
-       MLX5_ACCEL_IPSEC_CAP_ESP                = 1 << 2,
-       MLX5_ACCEL_IPSEC_CAP_IPV6               = 1 << 3,
-       MLX5_ACCEL_IPSEC_CAP_LSO                = 1 << 4,
-       MLX5_ACCEL_IPSEC_CAP_RX_NO_TRAILER      = 1 << 5,
-       MLX5_ACCEL_IPSEC_CAP_ESN                = 1 << 6,
-       MLX5_ACCEL_IPSEC_CAP_TX_IV_IS_ESN       = 1 << 7,
+       MLX5_ACCEL_IPSEC_CAP_ESP                = 1 << 1,
+       MLX5_ACCEL_IPSEC_CAP_IPV6               = 1 << 2,
+       MLX5_ACCEL_IPSEC_CAP_LSO                = 1 << 3,
+       MLX5_ACCEL_IPSEC_CAP_ESN                = 1 << 4,
 };
 
 #ifdef CONFIG_MLX5_EN_IPSEC