drm/i915: Invert if/else ladder for frequency read

Continue converting the driver to the convention of last version first,
extending it to the future platforms. Now, any GRAPHICS_VER >= 11 will
be handled by the first branch.

With the new ranges it's easier to see what platform a branch started to
be taken. Besides the >= 11 change, the branch taken for GRAPHICS_VER == 10
is also different, but currently there is no such platform in i915.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220908-if-ladder-v2-1-7a7b15545c93@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
index d5d1b04dbcad2ce714257b7fa792ace03a114a1e..93608c9349fd7ea0420eaf5a81d7ffa74faf24b0 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_clock_utils.c
@@ -78,77 +78,74 @@ static u32 read_clock_frequency(struct intel_uncore *uncore)
        u32 f19_2_mhz = 19200000;
        u32 f24_mhz = 24000000;
 
-       if (GRAPHICS_VER(uncore->i915) <= 4) {
-               /*
-                * PRMs say:
-                *
-                *     "The value in this register increments once every 16
-                *      hclks." (through the “Clocking Configuration”
-                *      (“CLKCFG”) MCHBAR register)
-                */
-               return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
-       } else if (GRAPHICS_VER(uncore->i915) <= 8) {
-               /*
-                * PRMs say:
-                *
-                *     "The PCU TSC counts 10ns increments; this timestamp
-                *      reflects bits 38:3 of the TSC (i.e. 80ns granularity,
-                *      rolling over every 1.5 hours).
-                */
-               return f12_5_mhz;
-       } else if (GRAPHICS_VER(uncore->i915) <= 9) {
+       if (GRAPHICS_VER(uncore->i915) >= 11) {
                u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
                u32 freq = 0;
 
+               /*
+                * First figure out the reference frequency. There are 2 ways
+                * we can compute the frequency, either through the
+                * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
+                * tells us which one we should use.
+                */
                if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
                        freq = read_reference_ts_freq(uncore);
                } else {
-                       freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
+                       u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
+
+                       if (GRAPHICS_VER(uncore->i915) >= 11)
+                               freq = gen11_get_crystal_clock_freq(uncore, c0);
+                       else
+                               freq = gen9_get_crystal_clock_freq(uncore, c0);
 
                        /*
                         * Now figure out how the command stream's timestamp
                         * register increments from this frequency (it might
                         * increment only every few clock cycle).
                         */
-                       freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
-                                     CTC_SHIFT_PARAMETER_SHIFT);
+                       freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
+                                     GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
                }
 
                return freq;
-       } else if (GRAPHICS_VER(uncore->i915) <= 12) {
+       } else if (GRAPHICS_VER(uncore->i915) >= 9) {
                u32 ctc_reg = intel_uncore_read(uncore, CTC_MODE);
                u32 freq = 0;
 
-               /*
-                * First figure out the reference frequency. There are 2 ways
-                * we can compute the frequency, either through the
-                * TIMESTAMP_OVERRIDE register or through RPM_CONFIG. CTC_MODE
-                * tells us which one we should use.
-                */
                if ((ctc_reg & CTC_SOURCE_PARAMETER_MASK) == CTC_SOURCE_DIVIDE_LOGIC) {
                        freq = read_reference_ts_freq(uncore);
                } else {
-                       u32 c0 = intel_uncore_read(uncore, RPM_CONFIG0);
-
-                       if (GRAPHICS_VER(uncore->i915) >= 11)
-                               freq = gen11_get_crystal_clock_freq(uncore, c0);
-                       else
-                               freq = gen9_get_crystal_clock_freq(uncore, c0);
+                       freq = IS_GEN9_LP(uncore->i915) ? f19_2_mhz : f24_mhz;
 
                        /*
                         * Now figure out how the command stream's timestamp
                         * register increments from this frequency (it might
                         * increment only every few clock cycle).
                         */
-                       freq >>= 3 - ((c0 & GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK) >>
-                                     GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT);
+                       freq >>= 3 - ((ctc_reg & CTC_SHIFT_PARAMETER_MASK) >>
+                                     CTC_SHIFT_PARAMETER_SHIFT);
                }
 
                return freq;
+       } else if (GRAPHICS_VER(uncore->i915) >= 5) {
+               /*
+                * PRMs say:
+                *
+                *     "The PCU TSC counts 10ns increments; this timestamp
+                *      reflects bits 38:3 of the TSC (i.e. 80ns granularity,
+                *      rolling over every 1.5 hours).
+                */
+               return f12_5_mhz;
+       } else {
+               /*
+                * PRMs say:
+                *
+                *     "The value in this register increments once every 16
+                *      hclks." (through the “Clocking Configuration”
+                *      (“CLKCFG”) MCHBAR register)
+                */
+               return RUNTIME_INFO(uncore->i915)->rawclk_freq * 1000 / 16;
        }
-
-       MISSING_CASE("Unknown gen, unable to read command streamer timestamp frequency\n");
-       return 0;
 }
 
 void intel_gt_init_clock_frequency(struct intel_gt *gt)