.x86_microcode_rev      = (revision),                   \
 }
 
+#define AMD_CPU_DESC(fam, model, stepping, revision) {         \
+       .x86_family             = (fam),                        \
+       .x86_vendor             = X86_VENDOR_AMD,               \
+       .x86_model              = (model),                      \
+       .x86_stepping           = (stepping),                   \
+       .x86_microcode_rev      = (revision),                   \
+}
+
 extern const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *match);
 extern bool x86_cpu_has_min_microcode_rev(const struct x86_cpu_desc *table);
 
 
 #include <asm/apic.h>
 #include <asm/cacheinfo.h>
 #include <asm/cpu.h>
+#include <asm/cpu_device_id.h>
 #include <asm/spec-ctrl.h>
 #include <asm/smp.h>
 #include <asm/numa.h>
        clear_rdrand_cpuid_bit(c);
 }
 
+static const struct x86_cpu_desc erratum_1386_microcode[] = {
+       AMD_CPU_DESC(0x17,  0x1, 0x2, 0x0800126e),
+       AMD_CPU_DESC(0x17, 0x31, 0x0, 0x08301052),
+};
+
 static void fix_erratum_1386(struct cpuinfo_x86 *c)
 {
        /*
         *
         * Affected parts all have no supervisor XSAVE states, meaning that
         * the XSAVEC instruction (which works fine) is equivalent.
+        *
+        * Clear the feature flag only on microcode revisions which
+        * don't have the fix.
         */
+       if (x86_cpu_has_min_microcode_rev(erratum_1386_microcode))
+               return;
+
        clear_cpu_cap(c, X86_FEATURE_XSAVES);
 }