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powerpc/8xx: Remove CPU6 ERRATA Workaround
authorChristophe Leroy <christophe.leroy@c-s.fr>
Fri, 12 Jan 2018 12:45:19 +0000 (13:45 +0100)
committerMichael Ellerman <mpe@ellerman.id.au>
Tue, 16 Jan 2018 12:47:12 +0000 (23:47 +1100)
CPU6 ERRATA affects only MPC860 revisions prior to C.0. Manufacturing
of those revisiosn was stopped in 1999-2000.
Therefore, it has been almost 20 years since this ERRATA has been
fixed in the silicon.

This patch removes the workaround for that ERRATA.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/configs/mpc866_ads_defconfig patch | blob | history
arch/powerpc/include/asm/reg_8xx.h patch | blob | history
arch/powerpc/kernel/head_8xx.S patch | blob | history
arch/powerpc/platforms/8xx/Kconfig patch | blob | history

diff --git a/arch/powerpc/configs/mpc866_ads_defconfig b/arch/powerpc/configs/mpc866_ads_defconfig
index f1f176c29fa3e932c1626453fc48824bd489fc41..5320735395e7fcadfc7775d23cd1a73b22f32f19 100644 (file)
--- a/arch/powerpc/configs/mpc866_ads_defconfig
+++ b/arch/powerpc/configs/mpc866_ads_defconfig
@@ -13,7 +13,6 @@ CONFIG_EXPERT=y
 CONFIG_PARTITION_ADVANCED=y
 CONFIG_MPC86XADS=y
 CONFIG_8xx_COPYBACK=y
-CONFIG_8xx_CPU6=y
 CONFIG_GEN_RTC=y
 CONFIG_HZ_1000=y
 CONFIG_MATH_EMULATION=y
diff --git a/arch/powerpc/include/asm/reg_8xx.h b/arch/powerpc/include/asm/reg_8xx.h
index 53a7e2955d3e9a82939a53c05211e52719f6112e..7192eece6c3e1f9a10f59b83cc90e39d7a33148a 100644 (file)
--- a/arch/powerpc/include/asm/reg_8xx.h
+++ b/arch/powerpc/include/asm/reg_8xx.h
@@ -66,86 +66,4 @@
 #define DC_DFWT                0x40000000      /* Data cache is forced write through */
 #define DC_LES         0x20000000      /* Caches are little endian mode */
 
-#ifdef CONFIG_8xx_CPU6
-#define do_mtspr_cpu6(rn, rn_addr, v)  \
-       do {                                                            \
-               int _reg_cpu6 = rn_addr, _tmp_cpu6;             \
-               asm volatile("stw %0, %1;"                              \
-                            "lwz %0, %1;"                              \
-                            "mtspr " __stringify(rn) ",%2" :           \
-                            : "r" (_reg_cpu6), "m"(_tmp_cpu6),         \
-                              "r" ((unsigned long)(v))                 \
-                            : "memory");                               \
-       } while (0)
-
-#define do_mtspr(rn, v)        asm volatile("mtspr " __stringify(rn) ",%0" :   \
-                                    : "r" ((unsigned long)(v))         \
-                                    : "memory")
-#define mtspr(rn, v) \
-       do {                                                            \
-               if (rn == SPRN_IMMR)                                    \
-                       do_mtspr_cpu6(rn, 0x3d30, v);                   \
-               else if (rn == SPRN_IC_CST)                             \
-                       do_mtspr_cpu6(rn, 0x2110, v);                   \
-               else if (rn == SPRN_IC_ADR)                             \
-                       do_mtspr_cpu6(rn, 0x2310, v);                   \
-               else if (rn == SPRN_IC_DAT)                             \
-                       do_mtspr_cpu6(rn, 0x2510, v);                   \
-               else if (rn == SPRN_DC_CST)                             \
-                       do_mtspr_cpu6(rn, 0x3110, v);                   \
-               else if (rn == SPRN_DC_ADR)                             \
-                       do_mtspr_cpu6(rn, 0x3310, v);                   \
-               else if (rn == SPRN_DC_DAT)                             \
-                       do_mtspr_cpu6(rn, 0x3510, v);                   \
-               else if (rn == SPRN_MI_CTR)                             \
-                       do_mtspr_cpu6(rn, 0x2180, v);                   \
-               else if (rn == SPRN_MI_AP)                              \
-                       do_mtspr_cpu6(rn, 0x2580, v);                   \
-               else if (rn == SPRN_MI_EPN)                             \
-                       do_mtspr_cpu6(rn, 0x2780, v);                   \
-               else if (rn == SPRN_MI_TWC)                             \
-                       do_mtspr_cpu6(rn, 0x2b80, v);                   \
-               else if (rn == SPRN_MI_RPN)                             \
-                       do_mtspr_cpu6(rn, 0x2d80, v);                   \
-               else if (rn == SPRN_MI_CAM)                             \
-                       do_mtspr_cpu6(rn, 0x2190, v);                   \
-               else if (rn == SPRN_MI_RAM0)                            \
-                       do_mtspr_cpu6(rn, 0x2390, v);                   \
-               else if (rn == SPRN_MI_RAM1)                            \
-                       do_mtspr_cpu6(rn, 0x2590, v);                   \
-               else if (rn == SPRN_MD_CTR)                             \
-                       do_mtspr_cpu6(rn, 0x3180, v);                   \
-               else if (rn == SPRN_M_CASID)                            \
-                       do_mtspr_cpu6(rn, 0x3380, v);                   \
-               else if (rn == SPRN_MD_AP)                              \
-                       do_mtspr_cpu6(rn, 0x3580, v);                   \
-               else if (rn == SPRN_MD_EPN)                             \
-                       do_mtspr_cpu6(rn, 0x3780, v);                   \
-               else if (rn == SPRN_M_TWB)                              \
-                       do_mtspr_cpu6(rn, 0x3980, v);                   \
-               else if (rn == SPRN_MD_TWC)                             \
-                       do_mtspr_cpu6(rn, 0x3b80, v);                   \
-               else if (rn == SPRN_MD_RPN)                             \
-                       do_mtspr_cpu6(rn, 0x3d80, v);                   \
-               else if (rn == SPRN_M_TW)                               \
-                       do_mtspr_cpu6(rn, 0x3f80, v);                   \
-               else if (rn == SPRN_MD_CAM)                             \
-                       do_mtspr_cpu6(rn, 0x3190, v);                   \
-               else if (rn == SPRN_MD_RAM0)                            \
-                       do_mtspr_cpu6(rn, 0x3390, v);                   \
-               else if (rn == SPRN_MD_RAM1)                            \
-                       do_mtspr_cpu6(rn, 0x3590, v);                   \
-               else if (rn == SPRN_DEC)                                \
-                       do_mtspr_cpu6(rn, 0x2c00, v);                   \
-               else if (rn == SPRN_TBWL)                               \
-                       do_mtspr_cpu6(rn, 0x3880, v);                   \
-               else if (rn == SPRN_TBWU)                               \
-                       do_mtspr_cpu6(rn, 0x3a80, v);                   \
-               else if (rn == SPRN_DPDR)                               \
-                       do_mtspr_cpu6(rn, 0x2d30, v);                   \
-               else                                                    \
-                       do_mtspr(rn, v);                                \
-       } while (0)
-#endif
-
 #endif /* _ASM_POWERPC_REG_8xx_H */
diff --git a/arch/powerpc/kernel/head_8xx.S b/arch/powerpc/kernel/head_8xx.S
index 4fee00d414e87c78d8a09ef3e9662b7bb7234c66..728b513c07b8d0065b60ed30b3965627a57f5224 100644 (file)
--- a/arch/powerpc/kernel/head_8xx.S
+++ b/arch/powerpc/kernel/head_8xx.S
@@ -33,23 +33,6 @@
 #include <asm/fixmap.h>
 #include <asm/export.h>
 
-/* Macro to make the code more readable. */
-#ifdef CONFIG_8xx_CPU6
-#define SPRN_MI_TWC_ADDR       0x2b80
-#define SPRN_MI_RPN_ADDR       0x2d80
-#define SPRN_MD_TWC_ADDR       0x3b80
-#define SPRN_MD_RPN_ADDR       0x3d80
-
-#define MTSPR_CPU6(spr, reg, treg)     \
-       li      treg, spr##_ADDR;       \
-       stw     treg, 12(r0);           \
-       lwz     treg, 12(r0);           \
-       mtspr   spr, reg
-#else
-#define MTSPR_CPU6(spr, reg, treg)     \
-       mtspr   spr, reg
-#endif
-
 #if CONFIG_TASK_SIZE <= 0x80000000 && CONFIG_PAGE_OFFSET >= 0x80000000
 /* By simply checking Address >= 0x80000000, we know if its a kernel address */
 #define SIMPLE_KERNEL_ADDRESS          1
@@ -326,7 +309,7 @@ SystemCall:
 #endif
 
 InstructionTLBMiss:
-#if defined(CONFIG_8xx_CPU6) || defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
+#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
        mtspr   SPRN_SPRG_SCRATCH2, r3
 #endif
        EXCEPTION_PROLOG_0
@@ -393,7 +376,7 @@ _ENTRY(ITLBMiss_cmp)
        /* Insert the APG into the TWC from the Linux PTE. */
        rlwimi  r11, r10, 0, 25, 26
        /* Load the MI_TWC with the attributes for this "segment." */
-       MTSPR_CPU6(SPRN_MI_TWC, r11, r3)        /* Set segment attributes */
+       mtspr   SPRN_MI_TWC, r11        /* Set segment attributes */
 
 #if defined (CONFIG_HUGETLB_PAGE) && defined (CONFIG_PPC_4K_PAGES)
        rlwimi  r10, r11, 1, MI_SPS16K
@@ -415,10 +398,10 @@ _ENTRY(ITLBMiss_cmp)
 #else
        rlwimi  r10, r11, 0, 0x0ff8     /* Set 24-27, clear 20-23,28 */
 #endif
-       MTSPR_CPU6(SPRN_MI_RPN, r10, r3)        /* Update TLB entry */
+       mtspr   SPRN_MI_RPN, r10        /* Update TLB entry */
 
        /* Restore registers */
-#if defined(CONFIG_8xx_CPU6) || defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
+#if defined(ITLB_MISS_KERNEL) || defined(CONFIG_HUGETLB_PAGE)
        mfspr   r3, SPRN_SPRG_SCRATCH2
 #endif
        EXCEPTION_EPILOG_0
@@ -512,7 +495,7 @@ _ENTRY(DTLBMiss_jmp)
         * It is bit 25 in the Linux PTE and bit 30 in the TWC
         */
        rlwimi  r11, r10, 32-5, 30, 30
-       MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
+       mtspr   SPRN_MD_TWC, r11
 
        /* In 4k pages mode, SPS (bit 28) in RPN must match PS[1] (bit 29)
         * In 16k pages mode, SPS is always 1 */
@@ -546,7 +529,7 @@ _ENTRY(DTLBMiss_jmp)
        rlwimi  r10, r11, 0, 24, 28     /* Set 24-27, clear 28 */
 #endif
        rlwimi  r10, r11, 0, 20, 20     /* clear 20 */
-       MTSPR_CPU6(SPRN_MD_RPN, r10, r3)        /* Update TLB entry */
+       mtspr   SPRN_MD_RPN, r10        /* Update TLB entry */
 
        /* Restore registers */
        mfspr   r3, SPRN_SPRG_SCRATCH2
@@ -684,12 +667,12 @@ DTLBMissIMMR:
        mtcr    r3
        /* Set 512k byte guarded page and mark it valid */
        li      r10, MD_PS512K | MD_GUARDED | MD_SVALID
-       MTSPR_CPU6(SPRN_MD_TWC, r10, r11)
+       mtspr   SPRN_MD_TWC, r10
        mfspr   r10, SPRN_IMMR                  /* Get current IMMR */
        rlwinm  r10, r10, 0, 0xfff80000         /* Get 512 kbytes boundary */
        ori     r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
                          _PAGE_PRESENT | _PAGE_NO_CACHE
-       MTSPR_CPU6(SPRN_MD_RPN, r10, r11)       /* Update TLB entry */
+       mtspr   SPRN_MD_RPN, r10        /* Update TLB entry */
 
        li      r11, RPN_PATTERN
        mtspr   SPRN_DAR, r11   /* Tag DAR */
@@ -701,11 +684,11 @@ DTLBMissLinear:
        mtcr    r3
        /* Set 8M byte page and mark it valid */
        li      r11, MD_PS8MEG | MD_SVALID
-       MTSPR_CPU6(SPRN_MD_TWC, r11, r3)
+       mtspr   SPRN_MD_TWC, r11
        rlwinm  r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
        ori     r10, r10, 0xf0 | MD_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
                          _PAGE_PRESENT
-       MTSPR_CPU6(SPRN_MD_RPN, r10, r11)       /* Update TLB entry */
+       mtspr   SPRN_MD_RPN, r10        /* Update TLB entry */
 
        li      r11, RPN_PATTERN
        mtspr   SPRN_DAR, r11   /* Tag DAR */
@@ -718,11 +701,11 @@ ITLBMissLinear:
        mtcr    r3
        /* Set 8M byte page and mark it valid */
        li      r11, MI_PS8MEG | MI_SVALID | _PAGE_EXEC
-       MTSPR_CPU6(SPRN_MI_TWC, r11, r3)
+       mtspr   SPRN_MI_TWC, r11
        rlwinm  r10, r10, 0, 0x0f800000 /* 8xx supports max 256Mb RAM */
        ori     r10, r10, 0xf0 | MI_SPS16K | _PAGE_SHARED | _PAGE_DIRTY | \
                          _PAGE_PRESENT
-       MTSPR_CPU6(SPRN_MI_RPN, r10, r11)       /* Update TLB entry */
+       mtspr   SPRN_MI_RPN, r10        /* Update TLB entry */
 
        mfspr   r3, SPRN_SPRG_SCRATCH2
        EXCEPTION_EPILOG_0
@@ -933,13 +916,6 @@ start_here:
         */
        lis     r6, swapper_pg_dir@ha
        tophys(r6,r6)
-#ifdef CONFIG_8xx_CPU6
-       lis     r4, cpu6_errata_word@h
-       ori     r4, r4, cpu6_errata_word@l
-       li      r3, 0x3f80
-       stw     r3, 12(r4)
-       lwz     r3, 12(r4)
-#endif
        mtspr   SPRN_M_TW, r6
        lis     r4,2f@h
        ori     r4,r4,2f@l
@@ -1094,12 +1070,6 @@ swapper_pg_dir:
 abatron_pteptrs:
        .space  8
 
-#ifdef CONFIG_8xx_CPU6
-       .globl  cpu6_errata_word
-cpu6_errata_word:
-       .space  16
-#endif
-
 #ifdef CONFIG_PPC_8xx_PERF_EVENT
        .globl  itlb_miss_counter
 itlb_miss_counter:
diff --git a/arch/powerpc/platforms/8xx/Kconfig b/arch/powerpc/platforms/8xx/Kconfig
index e2089d3de00c8dc82c7e4f1cf6e0b33e8af29adb..d408162d5af451472caf14fee7d641104084c2a5 100644 (file)
--- a/arch/powerpc/platforms/8xx/Kconfig
+++ b/arch/powerpc/platforms/8xx/Kconfig
@@ -116,18 +116,6 @@ config 8xx_GPIO
 
          If in doubt, say Y here.
 
-config 8xx_CPU6
-       bool "CPU6 Silicon Errata (860 Pre Rev. C)"
-       help
-         MPC860 CPUs, prior to Rev C have some bugs in the silicon, which
-         require workarounds for Linux (and most other OSes to work).  If you
-         get a BUG() very early in boot, this might fix the problem.  For
-         more details read the document entitled "MPC860 Family Device Errata
-         Reference" on Freescale's website.  This option also incurs a
-         performance hit.
-
-         If in doubt, say N here.
-
 config 8xx_CPU15
        bool "CPU15 Silicon Errata"
        depends on !HUGETLB_PAGE
ep93xx device tree rework repo: git://git.maquefel.me/linux.git