uint32_t last_non_cp;
uint32_t xcc1_kiq_start;
uint32_t xcc1_mec_ring0_start;
+ uint32_t aid1_sdma_start;
uint32_t max_assignment;
/* Per engine SDMA doorbell size in dword */
uint32_t sdma_doorbell_range;
/* 8 compute rings per GC. Max to 0x1CE */
AMDGPU_VEGA20_DOORBELL_XCC1_MEC_RING0_START = 0x197,
- AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x1CE,
+ /* AID1 SDMA: 0x1D0 ~ 0x1F7 */
+ AMDGPU_VEGA20_DOORBELL_AID1_sDMA_START = 0x1D0,
+
+ AMDGPU_VEGA20_DOORBELL_MAX_ASSIGNMENT = 0x1F7,
AMDGPU_VEGA20_DOORBELL_INVALID = 0xFFFF
} AMDGPU_VEGA20_DOORBELL_ASSIGNMENT;
ring->use_doorbell?"true":"false");
/* doorbell size is 2 dwords, get DWORD offset */
- ring->doorbell_index = adev->doorbell_index.sdma_engine[i] << 1;
+ if (aid_id > 0)
+ ring->doorbell_index =
+ (adev->doorbell_index.aid1_sdma_start << 1)
+ + adev->doorbell_index.sdma_doorbell_range
+ * (i - adev->sdma.num_inst_per_aid);
+ else
+ ring->doorbell_index =
+ adev->doorbell_index.sdma_engine[i] << 1;
ring->vm_hub = AMDGPU_MMHUB0(aid_id);
sprintf(ring->name, "sdma%d.%d", aid_id,
/* doorbell index of page queue is assigned right after
* gfx queue on the same instance
*/
- ring->doorbell_index = (adev->doorbell_index.sdma_engine[i] + 1) << 1;
+ if (aid_id > 0)
+ ring->doorbell_index =
+ ((adev->doorbell_index.aid1_sdma_start + 1) << 1)
+ + adev->doorbell_index.sdma_doorbell_range
+ * (i - adev->sdma.num_inst_per_aid);
+ else
+ ring->doorbell_index =
+ (adev->doorbell_index.sdma_engine[i] + 1) << 1;
ring->vm_hub = AMDGPU_MMHUB0(aid_id);
sprintf(ring->name, "page%d.%d", aid_id,