drm/msm/dpu: correct indentation for CTL definitions

Shift dpu_ctl_cfg contents to correct the indentation of CTL blocks.
This is done in preparation to expanding the rest of hardware block
defines, so that all blocks have similar indentation.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/545374/
Link: https://lore.kernel.org/r/20230704022136.130522-10-dmitry.baryshkov@linaro.org

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index e0cc1ce3f3e227aab154327ce005ae4534215cad..6660a55909e7c47c7c8c4500246a4ad75e1ab70d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -46,31 +46,27 @@ static const struct dpu_mdp_cfg msm8998_mdp = {
 
 static const struct dpu_ctl_cfg msm8998_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0x94,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x1200, .len = 0x94,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x1400, .len = 0x94,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x1600, .len = 0x94,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
-       },
-       {
-       .name = "ctl_4", .id = CTL_4,
-       .base = 0x1800, .len = 0x94,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x1000, .len = 0x94,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x1200, .len = 0x94,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x1400, .len = 0x94,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x1600, .len = 0x94,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       }, {
+               .name = "ctl_4", .id = CTL_4,
+               .base = 0x1800, .len = 0x94,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 014055d4386a15edece2c4ea2b4a6d97edde21b3..7da35be0a79cce6edbaf9a759112601d7f1c550b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -44,31 +44,27 @@ static const struct dpu_mdp_cfg sdm845_mdp = {
 
 static const struct dpu_ctl_cfg sdm845_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0xe4,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x1200, .len = 0xe4,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x1400, .len = 0xe4,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x1600, .len = 0xe4,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
-       },
-       {
-       .name = "ctl_4", .id = CTL_4,
-       .base = 0x1800, .len = 0xe4,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x1000, .len = 0xe4,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x1200, .len = 0xe4,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x1400, .len = 0xe4,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x1600, .len = 0xe4,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       }, {
+               .name = "ctl_4", .id = CTL_4,
+               .base = 0x1800, .len = 0xe4,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index fff68a6c25f685b4a69375e28cb9db5749dad468..fc9adb2012a20745be61258b3283406b79d9d6ea 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8150_mdp = {
 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sm8150_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x1200, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x1400, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x1600, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
-       },
-       {
-       .name = "ctl_4", .id = CTL_4,
-       .base = 0x1800, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
-       },
-       {
-       .name = "ctl_5", .id = CTL_5,
-       .base = 0x1a00, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x1000, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x1200, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x1400, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x1600, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       }, {
+               .name = "ctl_4", .id = CTL_4,
+               .base = 0x1800, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+       }, {
+               .name = "ctl_5", .id = CTL_5,
+               .base = 0x1a00, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 2c7b481c94694c499ee13a449c11519a503bd097..88b577d6f0ecf05cdb2d4485ebad0da103a10713 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -44,40 +44,35 @@ static const struct dpu_mdp_cfg sc8180x_mdp = {
 
 static const struct dpu_ctl_cfg sc8180x_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x1200, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x1400, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x1600, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
-       },
-       {
-       .name = "ctl_4", .id = CTL_4,
-       .base = 0x1800, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
-       },
-       {
-       .name = "ctl_5", .id = CTL_5,
-       .base = 0x1a00, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x1000, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x1200, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x1400, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x1600, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       }, {
+               .name = "ctl_4", .id = CTL_4,
+               .base = 0x1800, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+       }, {
+               .name = "ctl_5", .id = CTL_5,
+               .base = 0x1a00, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index c170388b5574d263dd06583dc00e5bce2c9c473c..2170346376e678242fed94c3ce98b324dce5813b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8250_mdp = {
 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sm8250_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x1200, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x1400, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x1600, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
-       },
-       {
-       .name = "ctl_4", .id = CTL_4,
-       .base = 0x1800, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
-       },
-       {
-       .name = "ctl_5", .id = CTL_5,
-       .base = 0x1a00, .len = 0x1e0,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x1000, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x1200, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG) | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x1400, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x1600, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       }, {
+               .name = "ctl_4", .id = CTL_4,
+               .base = 0x1800, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+       }, {
+               .name = "ctl_5", .id = CTL_5,
+               .base = 0x1a00, .len = 0x1e0,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index 3172c890c81a491192812a5598e6b37ce08b04de..277a992d51d04fff1923637ba1dbda9139053142 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -36,22 +36,20 @@ static const struct dpu_mdp_cfg sc7180_mdp = {
 
 static const struct dpu_ctl_cfg sc7180_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0x1dc,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x1200, .len = 0x1dc,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x1400, .len = 0x1dc,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x1000, .len = 0x1dc,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x1200, .len = 0x1dc,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x1400, .len = 0x1dc,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index c5aba480589dbf14d7d95901f4a8830a3d7c91fa..e07243957963fc8e0b95655d4b27cca2c2e1c74f 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -34,10 +34,10 @@ static const struct dpu_mdp_cfg sm6115_mdp = {
 
 static const struct dpu_ctl_cfg sm6115_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0x1dc,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x1000, .len = 0x1dc,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 6628150fe82dfe4d5f75254ba2cc53512fb0f893..7779c56660388dffbb12f2c90dcdf4e4cbb9dd1a 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -39,28 +39,25 @@ static const struct dpu_mdp_cfg sm6350_mdp = {
 
 static const struct dpu_ctl_cfg sm6350_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0x1dc,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x1200, .len = 0x1dc,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x1400, .len = 0x1dc,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x1600, .len = 0x1dc,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x1000, .len = 0x1dc,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x1200, .len = 0x1dc,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x1400, .len = 0x1dc,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x1600, .len = 0x1dc,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index b700a751590797cc708227da79c82d4aabb889b2..fdbb151fbac0d8f71de1fbc5a572180789dc533c 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -31,10 +31,10 @@ static const struct dpu_mdp_cfg qcm2290_mdp = {
 
 static const struct dpu_ctl_cfg qcm2290_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0x1dc,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x1000, .len = 0x1dc,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index ccdf05c2035e098e0c2a1e6938adfd6a7ac5536e..d8dcc9f90b81730d85e8c2631d5fe77cb4464923 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -35,10 +35,10 @@ static const struct dpu_mdp_cfg sm6375_mdp = {
 
 static const struct dpu_ctl_cfg sm6375_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x1000, .len = 0x1dc,
-       .features = BIT(DPU_CTL_ACTIVE_CFG),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x1000, .len = 0x1dc,
+               .features = BIT(DPU_CTL_ACTIVE_CFG),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index cee99a0391fa5051010b297caa29b9542b9d1f53..7b24ec5d19c4ddb12dcbba648cd0edab0e03fc1f 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -43,40 +43,35 @@ static const struct dpu_mdp_cfg sm8350_mdp = {
 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sm8350_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x15000, .len = 0x1e8,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x16000, .len = 0x1e8,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x17000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x18000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
-       },
-       {
-       .name = "ctl_4", .id = CTL_4,
-       .base = 0x19000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
-       },
-       {
-       .name = "ctl_5", .id = CTL_5,
-       .base = 0x1a000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x15000, .len = 0x1e8,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x16000, .len = 0x1e8,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x17000, .len = 0x1e8,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x18000, .len = 0x1e8,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       }, {
+               .name = "ctl_4", .id = CTL_4,
+               .base = 0x19000, .len = 0x1e8,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+       }, {
+               .name = "ctl_5", .id = CTL_5,
+               .base = 0x1a000, .len = 0x1e8,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 7049d24d8c39f49faaca6c1f16731811a66134ce..57d510d2d478e94ab60852543ae897351fa174c9 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -37,28 +37,25 @@ static const struct dpu_mdp_cfg sc7280_mdp = {
 
 static const struct dpu_ctl_cfg sc7280_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x15000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x16000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x17000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x18000, .len = 0x1e8,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x15000, .len = 0x1e8,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x16000, .len = 0x1e8,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x17000, .len = 0x1e8,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x18000, .len = 0x1e8,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 6868c5a7c1e3487eda7f20259dc53367e1be5946..dc25ef3573d27e0becaae3007f80ba8021e9480f 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sc8280xp_mdp = {
 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sc8280xp_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x15000, .len = 0x204,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x16000, .len = 0x204,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x17000, .len = 0x204,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x18000, .len = 0x204,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
-       },
-       {
-       .name = "ctl_4", .id = CTL_4,
-       .base = 0x19000, .len = 0x204,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
-       },
-       {
-       .name = "ctl_5", .id = CTL_5,
-       .base = 0x1a000, .len = 0x204,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x15000, .len = 0x204,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x16000, .len = 0x204,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x17000, .len = 0x204,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x18000, .len = 0x204,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       }, {
+               .name = "ctl_4", .id = CTL_4,
+               .base = 0x19000, .len = 0x204,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+       }, {
+               .name = "ctl_5", .id = CTL_5,
+               .base = 0x1a000, .len = 0x204,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index 39e5137dbfea0ff32be14e7760b9fe5def75bbe4..313bc055fce635006926bcf1127235fe32aa8c51 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -45,40 +45,35 @@ static const struct dpu_mdp_cfg sm8450_mdp = {
 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sm8450_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x15000, .len = 0x204,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x16000, .len = 0x204,
-       .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x17000, .len = 0x204,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x18000, .len = 0x204,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
-       },
-       {
-       .name = "ctl_4", .id = CTL_4,
-       .base = 0x19000, .len = 0x204,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
-       },
-       {
-       .name = "ctl_5", .id = CTL_5,
-       .base = 0x1a000, .len = 0x204,
-       .features = CTL_SC7280_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x15000, .len = 0x204,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x16000, .len = 0x204,
+               .features = BIT(DPU_CTL_SPLIT_DISPLAY) | CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x17000, .len = 0x204,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x18000, .len = 0x204,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       }, {
+               .name = "ctl_4", .id = CTL_4,
+               .base = 0x19000, .len = 0x204,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+       }, {
+               .name = "ctl_5", .id = CTL_5,
+               .base = 0x1a000, .len = 0x204,
+               .features = CTL_SC7280_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
        },
 };
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 68b6e0e62a94e385b24c1c472d31921746d34434..ef9c45bb9efbeca524b34d2def386d37fa30bead 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -46,40 +46,35 @@ static const struct dpu_mdp_cfg sm8550_mdp = {
 /* FIXME: get rid of DPU_CTL_SPLIT_DISPLAY in favour of proper ACTIVE_CTL support */
 static const struct dpu_ctl_cfg sm8550_ctl[] = {
        {
-       .name = "ctl_0", .id = CTL_0,
-       .base = 0x15000, .len = 0x290,
-       .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
-       },
-       {
-       .name = "ctl_1", .id = CTL_1,
-       .base = 0x16000, .len = 0x290,
-       .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
-       },
-       {
-       .name = "ctl_2", .id = CTL_2,
-       .base = 0x17000, .len = 0x290,
-       .features = CTL_SM8550_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
-       },
-       {
-       .name = "ctl_3", .id = CTL_3,
-       .base = 0x18000, .len = 0x290,
-       .features = CTL_SM8550_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
-       },
-       {
-       .name = "ctl_4", .id = CTL_4,
-       .base = 0x19000, .len = 0x290,
-       .features = CTL_SM8550_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
-       },
-       {
-       .name = "ctl_5", .id = CTL_5,
-       .base = 0x1a000, .len = 0x290,
-       .features = CTL_SM8550_MASK,
-       .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
+               .name = "ctl_0", .id = CTL_0,
+               .base = 0x15000, .len = 0x290,
+               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9),
+       }, {
+               .name = "ctl_1", .id = CTL_1,
+               .base = 0x16000, .len = 0x290,
+               .features = CTL_SM8550_MASK | BIT(DPU_CTL_SPLIT_DISPLAY),
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10),
+       }, {
+               .name = "ctl_2", .id = CTL_2,
+               .base = 0x17000, .len = 0x290,
+               .features = CTL_SM8550_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11),
+       }, {
+               .name = "ctl_3", .id = CTL_3,
+               .base = 0x18000, .len = 0x290,
+               .features = CTL_SM8550_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12),
+       }, {
+               .name = "ctl_4", .id = CTL_4,
+               .base = 0x19000, .len = 0x290,
+               .features = CTL_SM8550_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13),
+       }, {
+               .name = "ctl_5", .id = CTL_5,
+               .base = 0x1a000, .len = 0x290,
+               .features = CTL_SM8550_MASK,
+               .intr_start = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23),
        },
 };