wifi: rtw89: fw: extend program counter dump for Wi-Fi 7 chip

Extend FW program counter dump for Wi-Fi 7 chip.
They poll different addresses.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231204080751.15354-3-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/fw.c b/drivers/net/wireless/realtek/rtw89/fw.c
index 0b9c3c76b2732af569dd1255f5efa0d66ea4d8e8..81034b6ce4b040bce70da9a30fac16f7e232e2d8 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/fw.c
+++ b/drivers/net/wireless/realtek/rtw89/fw.c
@@ -957,16 +957,24 @@ static int rtw89_fw_download_main(struct rtw89_dev *rtwdev,
 
 static void rtw89_fw_prog_cnt_dump(struct rtw89_dev *rtwdev)
 {
+       enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
+       u32 addr = R_AX_DBG_PORT_SEL;
        u32 val32;
        u16 index;
 
+       if (chip_gen == RTW89_CHIP_BE) {
+               addr = R_BE_WLCPU_PORT_PC;
+               goto dump;
+       }
+
        rtw89_write32(rtwdev, R_AX_DBG_CTRL,
                      FIELD_PREP(B_AX_DBG_SEL0, FW_PROG_CNTR_DBG_SEL) |
                      FIELD_PREP(B_AX_DBG_SEL1, FW_PROG_CNTR_DBG_SEL));
        rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1, B_AX_SEL_0XC0_MASK, MAC_DBG_SEL);
 
+dump:
        for (index = 0; index < 15; index++) {
-               val32 = rtw89_read32(rtwdev, R_AX_DBG_PORT_SEL);
+               val32 = rtw89_read32(rtwdev, addr);
                rtw89_err(rtwdev, "[ERR]fw PC = 0x%x\n", val32);
                fsleep(10);
        }

diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index 1bd91c62678d9e56758ad2e3c32e20160849d514..690fa835c054077b8708e803aaccedd2cb8f1eaf 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -4023,6 +4023,8 @@
 #define B_BE_USB_HCISYS_PWR_STE_MASK GENMASK(3, 2)
 #define B_BE_PCIE_HCISYS_PWR_STE_MASK GENMASK(1, 0)
 
+#define R_BE_WLCPU_PORT_PC 0x03FC
+
 #define R_BE_DCPU_PLATFORM_ENABLE 0x0888
 #define B_BE_DCPU_SYM_DPLT_MEM_MUX_EN BIT(10)
 #define B_BE_DCPU_WARM_EN BIT(9)