arm64: dts: qcom: ipq9574: Enable Inline Crypto Engine for MMC

Add Inline Crypto Engine reg and clocks in MMC node and enable CQE
support as Inline Crypto Engine requires CQE to be enabled.

Signed-off-by: Vignesh Viswanathan <quic_viswanat@quicinc.com>
Link: https://lore.kernel.org/r/20231215095339.3055554-1-quic_viswanat@quicinc.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 5f83ee42a71942c9089e56781c9d839fcc542b2b..7f2e5cbf3bbb711afb8a9ae11402804f6613a18f 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -321,8 +321,10 @@
 
                sdhc_1: mmc@7804000 {
                        compatible = "qcom,ipq9574-sdhci", "qcom,sdhci-msm-v5";
-                       reg = <0x07804000 0x1000>, <0x07805000 0x1000>;
-                       reg-names = "hc", "cqhci";
+                       reg = <0x07804000 0x1000>,
+                             <0x07805000 0x1000>,
+                             <0x07808000 0x2000>;
+                       reg-names = "hc", "cqhci", "ice";
 
                        interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
@@ -330,9 +332,11 @@
 
                        clocks = <&gcc GCC_SDCC1_AHB_CLK>,
                                 <&gcc GCC_SDCC1_APPS_CLK>,
-                                <&xo_board_clk>;
-                       clock-names = "iface", "core", "xo";
+                                <&xo_board_clk>,
+                                <&gcc GCC_SDCC1_ICE_CORE_CLK>;
+                       clock-names = "iface", "core", "xo", "ice";
                        non-removable;
+                       supports-cqe;
                        status = "disabled";
                };