arm64: dts: Add support for Stratix 10 Software Virtual Platform
authorTeh Wen Ping <wen.ping.teh@intel.com>
Thu, 9 Jun 2022 02:55:00 +0000 (10:55 +0800)
committerDinh Nguyen <dinguyen@kernel.org>
Wed, 15 Jun 2022 14:51:44 +0000 (09:51 -0500)
Add Stratix 10 Software Virtual Platform device tree

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Teh Wen Ping <wen.ping.teh@intel.com>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
arch/arm64/Kconfig.platforms
arch/arm64/boot/dts/altera/Makefile
arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts [new file with mode: 0644]

index 4e6d635a1731ee157c57dd25f3ec7787ab47b9a0..aff8cbca811e96740a8098f0cf8f1c9df4c9a99a 100644 (file)
@@ -248,7 +248,8 @@ config ARCH_INTEL_SOCFPGA
        bool "Intel's SoCFPGA ARMv8 Families"
        help
          This enables support for Intel's SoCFPGA ARMv8 families:
-         Stratix 10 (ex. Altera), Agilex and eASIC N5X.
+         Stratix 10 (ex. Altera), Stratix10 Software Virtual Platform,
+         Agilex and eASIC N5X.
 
 config ARCH_SYNQUACER
        bool "Socionext SynQuacer SoC Family"
index 4db83fbeb115bcd46db381d951edcc19bf183e89..1bf0c472f6b4ac625e113d0010a940bf52626a12 100644 (file)
@@ -1,3 +1,4 @@
 # SPDX-License-Identifier: GPL-2.0-only
 dtb-$(CONFIG_ARCH_INTEL_SOCFPGA) += socfpga_stratix10_socdk.dtb \
-                               socfpga_stratix10_socdk_nand.dtb
+                               socfpga_stratix10_socdk_nand.dtb \
+                               socfpga_stratix10_swvp.dtb
diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_swvp.dts
new file mode 100644 (file)
index 0000000..a8db585
--- /dev/null
@@ -0,0 +1,117 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2022, Intel Corporation
+ */
+
+#include "socfpga_stratix10.dtsi"
+
+/ {
+       model = "SOCFPGA Stratix 10 SWVP";
+       compatible = "altr,socfpga-stratix10-swvp", "altr,socfpga-stratix10";
+
+       aliases {
+               serial0 = &uart0;
+               serial1 = &uart1;
+
+               timer0 = &timer0;
+               timer1 = &timer1;
+               timer2 = &timer2;
+               timer3 = &timer3;
+
+               ethernet0 = &gmac0;
+               ethernet1 = &gmac1;
+               ethernet2 = &gmac2;
+       };
+
+       chosen {
+               stdout-path = "serial1:115200n8";
+               linux,initrd-start = <0x10000000>;
+               linux,initrd-end = <0x125c8324>;
+       };
+
+       memory {
+               device_type = "memory";
+               reg = <0x0 0x0 0x0 0x80000000>;
+       };
+};
+
+&cpu0 {
+       enable-method = "spin-table";
+       cpu-release-addr = <0x0 0x0000fff8>;
+};
+
+&cpu1 {
+       enable-method = "spin-table";
+       cpu-release-addr = <0x0 0x0000fff8>;
+};
+
+&cpu2 {
+       enable-method = "spin-table";
+       cpu-release-addr = <0x0 0x0000fff8>;
+};
+
+&cpu3 {
+       enable-method = "spin-table";
+       cpu-release-addr = <0x0 0x0000fff8>;
+};
+
+&osc1 {
+       clock-frequency = <25000000>;
+};
+
+&gmac0 {
+       status = "okay";
+       phy-mode = "rgmii";
+       phy-addr = <0xffffffff>;
+       snps,max-mtu = <0x0>;
+};
+
+&gmac1 {
+       status = "okay";
+       phy-mode = "rgmii";
+       phy-addr = <0xffffffff>;
+};
+
+&gmac2 {
+       status = "okay";
+       phy-mode = "rgmii";
+       phy-addr = <0xffffffff>;
+};
+
+&mmc {
+       status = "okay";
+       altr,dw-mshc-ciu-div = <0x3>;
+       altr,dw-mshc-sdr-timing = <0x0 0x3>;
+       cap-sd-highspeed;
+       cap-mmc-highspeed;
+       broken-cd;
+       bus-width = <4>;
+};
+
+&uart0 {
+       status = "okay";
+};
+
+&uart1 {
+       status = "okay";
+};
+
+&usb0 {
+       clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
+       status = "okay";
+};
+
+&usb1 {
+       clocks = <&clkmgr STRATIX10_L4_MP_CLK>;
+       status = "okay";
+};
+
+&rst {
+       altr,modrst-offset = <0x20>;
+};
+
+&sysmgr {
+       reg = <0xffd12000 0x1000>;
+       interrupts = <0x0 0x10 0x4>;
+       cpu1-start-addr = <0xffd06230>;
+};