drm/i915/adlp: Fix typo for reference clock

Fix typo for reference clock from 24400 to 24000.

Bspec: 55409
Fixes: 626426ff9ce4 ("drm/i915/adl_p: Add cdclk support for ADL-P")
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Chaitanya Kumar Borah <chaitanya.kumar.borah@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230112094131.550252-1-chaitanya.kumar.borah@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 0c107a38f9d006799fc916de76f1b614ddbb24fa..7e16b655c83380186b6720622839bbd41555768a 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -1319,7 +1319,7 @@ static const struct intel_cdclk_vals adlp_cdclk_table[] = {
        { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
        { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
        { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
-       { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
+       { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
 
        { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
        { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },