selftests/powerpc/pmu/: Add interface test for mmcr1_comb field
authorAthira Rajeev <atrajeev@linux.vnet.ibm.com>
Thu, 27 Jan 2022 07:20:07 +0000 (12:50 +0530)
committerMichael Ellerman <mpe@ellerman.id.au>
Tue, 1 Mar 2022 12:40:16 +0000 (23:40 +1100)
The testcase uses event code "0x26880" to verify the settings for
different fields in Monitor Mode Control Register 1 (MMCR1). The field
include PMCxCOMB. Checks if this field are translated correctly via perf
interface to MMCR1

Add selftest for mmcr1 comb field.

Signed-off-by: Athira Rajeev <atrajeev@linux.vnet.ibm.com>
[mpe: Add error checking, drop GET_MMCR_FIELD, add to .gitignore]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220127072012.662451-16-kjain@linux.ibm.com
tools/testing/selftests/powerpc/pmu/sampling_tests/.gitignore
tools/testing/selftests/powerpc/pmu/sampling_tests/Makefile
tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_comb_test.c [new file with mode: 0644]

index 1a3b7323acd133e6425db924c22911e0e7b8d7e9..f0ad66d78ee0b3d4264a8021eee47d906c796699 100644 (file)
@@ -4,3 +4,4 @@ mmcr0_pmccext_test
 mmcr0_pmcjce_test
 mmcr0_fc56_pmc1ce_test
 mmcr0_fc56_pmc56_test
+mmcr1_comb_test
index 790a7ff21a9052769268eb4c8c9e24c80765157b..da87ffddc56847587350e5819e9b144e169f5421 100644 (file)
@@ -2,7 +2,8 @@
 CFLAGS += -m64
 
 TEST_GEN_PROGS := mmcr0_exceptionbits_test mmcr0_cc56run_test mmcr0_pmccext_test \
-                  mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test
+                  mmcr0_pmcjce_test mmcr0_fc56_pmc1ce_test mmcr0_fc56_pmc56_test \
+                  mmcr1_comb_test
 
 top_srcdir = ../../../../../..
 include ../../../lib.mk
diff --git a/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_comb_test.c b/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcr1_comb_test.c
new file mode 100644 (file)
index 0000000..5aea649
--- /dev/null
@@ -0,0 +1,66 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2022, Athira Rajeev, IBM Corp.
+ */
+
+#include <stdio.h>
+#include <stdlib.h>
+
+#include "../event.h"
+#include "misc.h"
+#include "utils.h"
+
+/* All successful D-side store dispatches for this thread that were L2 Miss */
+#define EventCode 0x46880
+
+extern void thirty_two_instruction_loop_with_ll_sc(u64 loops, u64 *ll_sc_target);
+
+/*
+ * A perf sampling test for mmcr1
+ * fields : comb.
+ */
+static int mmcr1_comb(void)
+{
+       struct event event;
+       u64 *intr_regs;
+       u64 dummy;
+
+       /* Check for platform support for the test */
+       SKIP_IF(check_pvr_for_sampling_tests());
+
+       /* Init the event for the sampling test */
+       event_init_sampling(&event, EventCode);
+       event.attr.sample_regs_intr = platform_extended_mask;
+       FAIL_IF(event_open(&event));
+       event.mmap_buffer = event_sample_buf_mmap(event.fd, 1);
+
+       FAIL_IF(event_enable(&event));
+
+       /* workload to make the event overflow */
+       thirty_two_instruction_loop_with_ll_sc(10000000, &dummy);
+
+       FAIL_IF(event_disable(&event));
+
+       /* Check for sample count */
+       FAIL_IF(!collect_samples(event.mmap_buffer));
+
+       intr_regs = get_intr_regs(&event, event.mmap_buffer);
+
+       /* Check for intr_regs */
+       FAIL_IF(!intr_regs);
+
+       /*
+        * Verify that comb field match with
+        * corresponding event code fields
+        */
+       FAIL_IF(EV_CODE_EXTRACT(event.attr.config, comb) !=
+               get_mmcr1_comb(get_reg_value(intr_regs, "MMCR1"), 4));
+
+       event_close(&event);
+       return 0;
+}
+
+int main(void)
+{
+       return test_harness(mmcr1_comb, "mmcr1_comb");
+}