drm/amd/display: Disable DC Mode Capping On DCN321

Why:
Limiting clocks to DC mode max results in some
display modes to no longer be supported

How:
Disable the path that limits the clock values

Fixes: 3b718dcaf163 ("drm/amd/display: Filter out AC mode frequencies on DC mode systems")
Reviewed-by: Martin Leung <martin.leung@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Austin Zheng <austin.zheng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
index 28320c608aebd2783c5febd1587e8f7b40fcca84..ca409a441953d800789a14c342f05a7ed23cb5c4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn321/dcn321_resource.c
@@ -731,6 +731,7 @@ static const struct dc_debug_options debug_defaults_drv = {
        .fpo_vactive_min_active_margin_us = 200,
        .fpo_vactive_max_blank_us = 1000,
        .enable_legacy_fast_update = false,
+       .disable_dc_mode_overwrite = true,
 };
 
 static struct dce_aux *dcn321_aux_engine_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
index 190776063f46a7ad17c1f7b923d440cc97508473..b26fcf86014c70cff2e8805984f83f94eeec80f7 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn321/dcn321_fpu.c
@@ -415,11 +415,11 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk
 
        if (max_clk_data.fclk_mhz == 0)
                max_clk_data.fclk_mhz = max_clk_data.dcfclk_mhz *
-                               dcn3_2_soc.pct_ideal_sdp_bw_after_urgent /
-                               dcn3_2_soc.pct_ideal_fabric_bw_after_urgent;
+                               dcn3_21_soc.pct_ideal_sdp_bw_after_urgent /
+                               dcn3_21_soc.pct_ideal_fabric_bw_after_urgent;
 
        if (max_clk_data.phyclk_mhz == 0)
-               max_clk_data.phyclk_mhz = dcn3_2_soc.clock_limits[0].phyclk_mhz;
+               max_clk_data.phyclk_mhz = dcn3_21_soc.clock_limits[0].phyclk_mhz;
 
        *num_entries = 0;
        entry.dispclk_mhz = max_clk_data.dispclk_mhz;
@@ -427,8 +427,8 @@ static int build_synthetic_soc_states(bool disable_dc_mode_overwrite, struct clk
        entry.dppclk_mhz = max_clk_data.dppclk_mhz;
        entry.dtbclk_mhz = max_clk_data.dtbclk_mhz;
        entry.phyclk_mhz = max_clk_data.phyclk_mhz;
-       entry.phyclk_d18_mhz = dcn3_2_soc.clock_limits[0].phyclk_d18_mhz;
-       entry.phyclk_d32_mhz = dcn3_2_soc.clock_limits[0].phyclk_d32_mhz;
+       entry.phyclk_d18_mhz = dcn3_21_soc.clock_limits[0].phyclk_d18_mhz;
+       entry.phyclk_d32_mhz = dcn3_21_soc.clock_limits[0].phyclk_d32_mhz;
 
        // Insert all the DCFCLK STAs
        for (i = 0; i < num_dcfclk_stas; i++) {