ARM: at91: pm: add sama7g5 ddr controller

Add SAMA7G5 DDR controller to the list of DDR controller compatibles.
At the moment there is no standby support. Adapt the code for this.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Link: https://lore.kernel.org/r/20210415105010.569620-18-claudiu.beznea@microchip.com

diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 65e13769cf50f968b0e90585607aa4088163b4a7..5dc942a2012d9d99db7eb9ff4af030e60747bb8e 100644 (file)
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -548,6 +548,7 @@ static const struct of_device_id ramc_ids[] __initconst = {
        { .compatible = "atmel,at91sam9260-sdramc", .data = &ramc_infos[1] },
        { .compatible = "atmel,at91sam9g45-ddramc", .data = &ramc_infos[2] },
        { .compatible = "atmel,sama5d3-ddramc", .data = &ramc_infos[3] },
+       { .compatible = "microchip,sama7g5-uddrc", },
        { /*sentinel*/ }
 };
 
@@ -565,9 +566,11 @@ static __init void at91_dt_ramc(void)
                        panic(pr_fmt("unable to map ramc[%d] cpu registers\n"), idx);
 
                ramc = of_id->data;
-               if (!standby)
-                       standby = ramc->idle;
-               soc_pm.data.memctrl = ramc->memctrl;
+               if (ramc) {
+                       if (!standby)
+                               standby = ramc->idle;
+                       soc_pm.data.memctrl = ramc->memctrl;
+               }
 
                idx++;
        }