ARM: 9004/1: debug: Split waituart to CTS and TXRDY

This patch was triggered by a remark from Russell that
introducing a call to the waituart (needed to fix debug prints
on the Qualcomm platforms) was dangerous because in some cases
this will involve waiting for a modem CTS (clear to send)
signal, and debug messages would maybe not work on platforms
with no modem connected to the UART port: they will just
hang waiting for the modem to assert CTS and this might never
happen.

Looking through all UART debug drivers implementing the waituart
macro I discovered that all users except two actually use this
macro to check if the UART is ready for TX, let's call this
TXRDY.

Only two debug UART drivers actually check for CTS:
- arch/arm/include/debug/8250.S
- arch/arm/include/debug/tegra.S

The former is very significant since the 8250 is possibly
the most common UART on the planet.

We have the following problem: the semantics of waituart are
ambiguous making it dangerous to introduce the macro to debug
code fixing debug prints for Qualcomm. To start to pry this
problem apart, this patch does the following:

- Convert all debug UART drivers to define two macros:

  - waituartcts with the clear semantic to wait for CTS
    to be asserted

  - waituarttxrdy with the clear semantic to wait for the TX
    capability of the UART to be ready

- When doing this take care to assign the right function to
  each drivers macro, so they now do exactly the above.

- Update the three sites in the kernel invoking the waituart
  macro to call waituartcts/waituarttxrdy in sequence, so that
  the functional impact on the kernel should be zero.

After this we can start to change the code sites using this
code to do the right thing.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/arch/arm/boot/compressed/debug.S b/arch/arm/boot/compressed/debug.S
index 6bf2917a46214f09215e35debe7ddfdc5df4d5d3..97f4e74692e897cdc0a90544efe6a7bf526e7bc4 100644 (file)
--- a/arch/arm/boot/compressed/debug.S
+++ b/arch/arm/boot/compressed/debug.S
@@ -8,7 +8,8 @@
 
 ENTRY(putc)
        addruart r1, r2, r3
-       waituart r3, r1
+       waituartcts r3, r1
+       waituarttxrdy r3, r1
        senduart r0, r1
        busyuart r3, r1
        mov      pc, lr

diff --git a/arch/arm/include/debug/8250.S b/arch/arm/include/debug/8250.S
index e4a036f082c29c722e69f0cfbb0b9230c0653b56..769246d87fffbdb2ea186b89c93d76d1221b7800 100644 (file)
--- a/arch/arm/include/debug/8250.S
+++ b/arch/arm/include/debug/8250.S
@@ -45,7 +45,10 @@
                bne     1002b
                .endm
 
-               .macro  waituart,rd,rx
+               .macro  waituarttxrdy,rd,rx
+               .endm
+
+               .macro  waituartcts,rd,rx
 #ifdef CONFIG_DEBUG_UART_8250_FLOW_CONTROL
 1001:          load    \rd, [\rx, #UART_MSR << UART_SHIFT]
                tst     \rd, #UART_MSR_CTS

diff --git a/arch/arm/include/debug/asm9260.S b/arch/arm/include/debug/asm9260.S
index 0da1eb6253318dcd18c4c81eb896e865712041c1..5a0ce145c44abacceea3983e99d957d27b4edcae 100644 (file)
--- a/arch/arm/include/debug/asm9260.S
+++ b/arch/arm/include/debug/asm9260.S
@@ -11,7 +11,10 @@
                ldr     \rv, = CONFIG_DEBUG_UART_VIRT
                .endm
 
-               .macro  waituart,rd,rx
+               .macro  waituarttxrdy,rd,rx
+               .endm
+
+               .macro  waituartcts,rd,rx
                .endm
 
                .macro  senduart,rd,rx

diff --git a/arch/arm/include/debug/at91.S b/arch/arm/include/debug/at91.S
index 6c91cbaaa20be8a7a943703ae062a54c88279c8b..17722824e2f2222d7f0e78e0d0e05cbf860e2a39 100644 (file)
--- a/arch/arm/include/debug/at91.S
+++ b/arch/arm/include/debug/at91.S
@@ -19,12 +19,15 @@
        strb    \rd, [\rx, #(AT91_DBGU_THR)]            @ Write to Transmitter Holding Register
        .endm
 
-       .macro  waituart,rd,rx
+       .macro  waituarttxrdy,rd,rx
 1001:  ldr     \rd, [\rx, #(AT91_DBGU_SR)]             @ Read Status Register
        tst     \rd, #AT91_DBGU_TXRDY                   @ DBGU_TXRDY = 1 when ready to transmit
        beq     1001b
        .endm
 
+       .macro  waituartcts,rd,rx
+       .endm
+
        .macro  busyuart,rd,rx
 1001:  ldr     \rd, [\rx, #(AT91_DBGU_SR)]             @ Read Status Register
        tst     \rd, #AT91_DBGU_TXEMPTY                 @ DBGU_TXEMPTY = 1 when transmission complete

diff --git a/arch/arm/include/debug/bcm63xx.S b/arch/arm/include/debug/bcm63xx.S
index 06a8962273960078c3749663396a0550a9d158db..da65abb6738dba43de5af0c8ba0f5c3e00d84a44 100644 (file)
--- a/arch/arm/include/debug/bcm63xx.S
+++ b/arch/arm/include/debug/bcm63xx.S
@@ -17,12 +17,15 @@
        strb    \rd, [\rx, #UART_FIFO_REG]
        .endm
 
-       .macro  waituart, rd, rx
+       .macro  waituarttxrdy, rd, rx
 1001:  ldr     \rd, [\rx, #UART_IR_REG]
        tst     \rd, #(1 << UART_IR_TXEMPTY)
        beq     1001b
        .endm
 
+       .macro  waituartcts, rd, rx
+       .endm
+
        .macro  busyuart, rd, rx
 1002:  ldr     \rd, [\rx, #UART_IR_REG]
        tst     \rd, #(1 << UART_IR_TXTRESH)

diff --git a/arch/arm/include/debug/brcmstb.S b/arch/arm/include/debug/brcmstb.S
index 132a20c4a67691683edd6a14e43f7e637b562a3a..7ffe66993029bbf99a221c6b10c86fec46463297 100644 (file)
--- a/arch/arm/include/debug/brcmstb.S
+++ b/arch/arm/include/debug/brcmstb.S
@@ -142,7 +142,10 @@ ARM_BE8(   rev     \rd, \rd )
                bne     1002b
                .endm
 
-               .macro  waituart,rd,rx
+               .macro  waituarttxrdy,rd,rx
+               .endm
+
+               .macro  waituartcts,rd,rx
                .endm
 
 /*

diff --git a/arch/arm/include/debug/clps711x.S b/arch/arm/include/debug/clps711x.S
index 774a67ac3877dd6baebb2dc8eefc96938feef191..a983d12a65159fc551087882d997e699a5748329 100644 (file)
--- a/arch/arm/include/debug/clps711x.S
+++ b/arch/arm/include/debug/clps711x.S
@@ -20,7 +20,10 @@
        ldr     \rp, =CLPS711X_UART_PADDR
        .endm
 
-       .macro  waituart,rd,rx
+       .macro  waituartcts,rd,rx
+       .endm
+
+       .macro  waituarttxrdy,rd,rx
        .endm
 
        .macro  senduart,rd,rx

diff --git a/arch/arm/include/debug/dc21285.S b/arch/arm/include/debug/dc21285.S
index d7e8c71706abd9293174e8727b6bc2c2865893bf..4ec0e5e3170480849c95337009d3196a4afa2cfa 100644 (file)
--- a/arch/arm/include/debug/dc21285.S
+++ b/arch/arm/include/debug/dc21285.S
@@ -34,5 +34,8 @@
                bne     1001b
                .endm
 
-               .macro  waituart,rd,rx
+               .macro  waituartcts,rd,rx
+               .endm
+
+               .macro  waituarttxrdy,rd,rx
                .endm

diff --git a/arch/arm/include/debug/digicolor.S b/arch/arm/include/debug/digicolor.S
index 256f5f4da2759d4a1e4f72ef3c5f0b9ab3c90478..443674cad76a8cbda09f69123a8be1bde17cf027 100644 (file)
--- a/arch/arm/include/debug/digicolor.S
+++ b/arch/arm/include/debug/digicolor.S
@@ -21,7 +21,10 @@
                strb    \rd, [\rx, #UA0_EMI_REC]
                .endm
 
-               .macro  waituart,rd,rx
+               .macro  waituartcts,rd,rx
+               .endm
+
+               .macro  waituarttxrdy,rd,rx
                .endm
 
        .macro  busyuart,rd,rx

diff --git a/arch/arm/include/debug/efm32.S b/arch/arm/include/debug/efm32.S
index 5ed5028306f4a605bff81df0782e5a8346773e45..b0083d6e31e80aac07529f8584ac3ae55f3dae7b 100644 (file)
--- a/arch/arm/include/debug/efm32.S
+++ b/arch/arm/include/debug/efm32.S
@@ -29,7 +29,10 @@
                strb    \rd, [\rx, #UARTn_TXDATA]
                .endm
 
-               .macro  waituart,rd,rx
+               .macro  waituartcts,rd,rx
+               .endm
+
+               .macro  waituarttxrdy,rd,rx
 1001:          ldr     \rd, [\rx, #UARTn_STATUS]
                tst     \rd, #UARTn_STATUS_TXBL
                beq     1001b

diff --git a/arch/arm/include/debug/icedcc.S b/arch/arm/include/debug/icedcc.S
index 74a0dd036a175edac05d931db5f132e9e18f5b53..d5e65da8a6874398973e9074e8a393fed24cc7b7 100644 (file)
--- a/arch/arm/include/debug/icedcc.S
+++ b/arch/arm/include/debug/icedcc.S
@@ -23,7 +23,10 @@
                beq     1001b
                .endm
 
-               .macro  waituart, rd, rx
+               .macro  waituartcts, rd, rx
+               .endm
+
+               .macro  waituarttxrdy, rd, rx
                mov     \rd, #0x2000000
 1001:
                subs    \rd, \rd, #1
@@ -47,7 +50,10 @@
                beq     1001b
                .endm
 
-               .macro  waituart, rd, rx
+               .macro  waituartcts, rd, rx
+               .endm
+
+               .macro  waituarttxrdy, rd, rx
                mov     \rd, #0x10000000
 1001:
                subs    \rd, \rd, #1
@@ -72,7 +78,10 @@
 
                .endm
 
-               .macro  waituart, rd, rx
+               .macro  waituartcts, rd, rx
+               .endm
+
+               .macro  waituarttxrdy, rd, rx
                mov     \rd, #0x2000000
 1001:
                subs    \rd, \rd, #1

diff --git a/arch/arm/include/debug/imx.S b/arch/arm/include/debug/imx.S
index 1c1b9d1da4c8f5e28ece495f8c1d1c6bcce8807b..bb7b9550580c4857a884a8f6c77ac71fd747bd30 100644 (file)
--- a/arch/arm/include/debug/imx.S
+++ b/arch/arm/include/debug/imx.S
@@ -35,7 +35,10 @@
                str     \rd, [\rx, #0x40]       @ TXDATA
                .endm
 
-               .macro  waituart,rd,rx
+               .macro  waituartcts,rd,rx
+               .endm
+
+               .macro  waituarttxrdy,rd,rx
                .endm
 
                .macro  busyuart,rd,rx

diff --git a/arch/arm/include/debug/meson.S b/arch/arm/include/debug/meson.S
index 1e501a0054aea10ee77829ee6c9c32fcd6a64035..7b60e4401225e7ebdff81f367883765f1017324a 100644 (file)
--- a/arch/arm/include/debug/meson.S
+++ b/arch/arm/include/debug/meson.S
@@ -25,7 +25,10 @@
        beq     1002b
        .endm
 
-       .macro  waituart,rd,rx
+       .macro  waituartcts,rd,rx
+       .endm
+
+       .macro  waituarttxrdy,rd,rx
 1001:  ldr     \rd, [\rx, #MESON_AO_UART_STATUS]
        tst     \rd, #MESON_AO_UART_TX_FIFO_FULL
        bne     1001b

diff --git a/arch/arm/include/debug/msm.S b/arch/arm/include/debug/msm.S
index 9405b71461daf1aebe3968835a6c2682159d86f3..530edc74f9a3b0dbde9404a880618381fb242ba7 100644 (file)
--- a/arch/arm/include/debug/msm.S
+++ b/arch/arm/include/debug/msm.S
@@ -17,7 +17,10 @@ ARM_BE8(rev  \rd, \rd )
        str     \rd, [\rx, #0x70]
        .endm
 
-       .macro  waituart, rd, rx
+       .macro  waituartcts,rd,rx
+       .endm
+
+       .macro  waituarttxrdy, rd, rx
        @ check for TX_EMT in UARTDM_SR
        ldr     \rd, [\rx, #0x08]
 ARM_BE8(rev     \rd, \rd )

diff --git a/arch/arm/include/debug/omap2plus.S b/arch/arm/include/debug/omap2plus.S
index b5696a33ba0f524b26dbd41b4cbc18064b01e969..0680be6c79d35960f96d83a4a2e50e65e4c1d406 100644 (file)
--- a/arch/arm/include/debug/omap2plus.S
+++ b/arch/arm/include/debug/omap2plus.S
@@ -75,5 +75,8 @@ omap_uart_lsr:        .word   0
                bne     1001b
                .endm
 
-               .macro  waituart,rd,rx
+               .macro  waituartcts,rd,rx
+               .endm
+
+               .macro  waituarttxrdy,rd,rx
                .endm

diff --git a/arch/arm/include/debug/pl01x.S b/arch/arm/include/debug/pl01x.S
index a2a553afe7b89e4409c7ba5b583d8011bb0ff0c3..0c7bfa4c10dbf855f7e9574513ee595c79c9e765 100644 (file)
--- a/arch/arm/include/debug/pl01x.S
+++ b/arch/arm/include/debug/pl01x.S
@@ -26,7 +26,10 @@
                strb    \rd, [\rx, #UART01x_DR]
                .endm
 
-               .macro  waituart,rd,rx
+               .macro  waituartcts,rd,rx
+               .endm
+
+               .macro  waituarttxrdy,rd,rx
 1001:          ldr     \rd, [\rx, #UART01x_FR]
  ARM_BE8(      rev     \rd, \rd )
                tst     \rd, #UART01x_FR_TXFF

diff --git a/arch/arm/include/debug/renesas-scif.S b/arch/arm/include/debug/renesas-scif.S
index 25f06663a9a4e2c1b2f569b8bb10b5c503a78e83..8e433e981bbe867491a61529d9a57c96b51532f2 100644 (file)
--- a/arch/arm/include/debug/renesas-scif.S
+++ b/arch/arm/include/debug/renesas-scif.S
@@ -33,7 +33,10 @@
        ldr     \rv, =SCIF_VIRT
        .endm
 
-       .macro  waituart, rd, rx
+       .macro  waituartcts,rd,rx
+       .endm
+
+       .macro  waituarttxrdy, rd, rx
 1001:  ldrh    \rd, [\rx, #FSR]
        tst     \rd, #TDFE
        beq     1001b

diff --git a/arch/arm/include/debug/sa1100.S b/arch/arm/include/debug/sa1100.S
index 6109e6058e5b3eb80cd9e58a8e871e760cc4f245..7968ea52df3d5375f8ce414d465b73bebbf2e862 100644 (file)
--- a/arch/arm/include/debug/sa1100.S
+++ b/arch/arm/include/debug/sa1100.S
@@ -51,7 +51,10 @@
                str     \rd, [\rx, #UTDR]
                .endm
 
-               .macro  waituart,rd,rx
+               .macro  waituartcts,rd,rx
+               .endm
+
+               .macro  waituarttxrdy,rd,rx
 1001:          ldr     \rd, [\rx, #UTSR1]
                tst     \rd, #UTSR1_TNF
                beq     1001b

diff --git a/arch/arm/include/debug/samsung.S b/arch/arm/include/debug/samsung.S
index 69201d7fb48f6443d0ec8e5bb474764d947275b0..ab474d564a90944c6c42882688931d38d14556df 100644 (file)
--- a/arch/arm/include/debug/samsung.S
+++ b/arch/arm/include/debug/samsung.S
@@ -69,7 +69,10 @@ ARM_BE8(rev \rd, \rd)
 1002:          @ exit busyuart
        .endm
 
-       .macro  waituart,rd,rx
+       .macro  waituartcts,rd,rx
+       .endm
+
+       .macro  waituarttxrdy,rd,rx
                ldr     \rd, [\rx, # S3C2410_UFCON]
 ARM_BE8(rev \rd, \rd)
                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?

diff --git a/arch/arm/include/debug/sirf.S b/arch/arm/include/debug/sirf.S
index e73e4de0a015312fe01d344972a7998b8c6bd4d8..3612c7b9cbe71575b09bb9d4ee4c069febed6504 100644 (file)
--- a/arch/arm/include/debug/sirf.S
+++ b/arch/arm/include/debug/sirf.S
@@ -29,7 +29,10 @@
        .macro  busyuart,rd,rx
        .endm
 
-       .macro  waituart,rd,rx
+       .macro  waituartcts,rd,rx
+       .endm
+
+       .macro  waituarttxrdy,rd,rx
 1001:  ldr     \rd, [\rx, #SIRF_LLUART_TXFIFO_STATUS]
        tst     \rd, #SIRF_LLUART_TXFIFO_EMPTY
        beq     1001b

diff --git a/arch/arm/include/debug/sti.S b/arch/arm/include/debug/sti.S
index 6b42c91f217d4019f392eac6d4eab53f210ea259..72d0525118908804f9d24b751211ae191dbe9100 100644 (file)
--- a/arch/arm/include/debug/sti.S
+++ b/arch/arm/include/debug/sti.S
@@ -45,7 +45,10 @@
                 strb    \rd, [\rx, #ASC_TX_BUF_OFF]
                 .endm
 
-                .macro  waituart,rd,rx
+               .macro  waituartcts,rd,rx
+               .endm
+
+                .macro  waituarttxrdy,rd,rx
 1001:           ldr     \rd, [\rx, #ASC_STA_OFF]
                 tst     \rd, #ASC_STA_TX_FULL
                 bne     1001b

diff --git a/arch/arm/include/debug/stm32.S b/arch/arm/include/debug/stm32.S
index f3c4a37210ed5ea8441374f5fe94417574b8a67c..b6d9df30e37d2cf853be44cb82bf776117b94113 100644 (file)
--- a/arch/arm/include/debug/stm32.S
+++ b/arch/arm/include/debug/stm32.S
@@ -27,7 +27,10 @@
        strb    \rd, [\rx, #STM32_USART_TDR_OFF]
 .endm
 
-.macro  waituart,rd,rx
+.macro waituartcts,rd,rx
+.endm
+
+.macro  waituarttxrdy,rd,rx
 1001:  ldr     \rd, [\rx, #(STM32_USART_SR_OFF)]       @ Read Status Register
        tst     \rd, #STM32_USART_TXE                   @ TXE = 1 = tx empty
        beq     1001b

diff --git a/arch/arm/include/debug/tegra.S b/arch/arm/include/debug/tegra.S
index 2148d0f8859194f1ee6928dfb8d995a2899bf134..2bca6358cdd06a2c138d2783962bb2e84a3d5a25 100644 (file)
--- a/arch/arm/include/debug/tegra.S
+++ b/arch/arm/include/debug/tegra.S
@@ -178,7 +178,7 @@
 1002:
                .endm
 
-               .macro  waituart, rd, rx
+               .macro  waituartcts, rd, rx
 #ifdef FLOW_CONTROL
                cmp     \rx, #0
                beq     1002f
@@ -189,6 +189,9 @@
 #endif
                .endm
 
+               .macro  waituarttxrdy,rd,rx
+               .endm
+
 /*
  * Storage for the state maintained by the macros above.
  *

diff --git a/arch/arm/include/debug/vf.S b/arch/arm/include/debug/vf.S
index 854d9bd8277019e50de31cc6823278ef343afaf5..035bcbf117ab3877621cee71c2a06e0a7ae4d1ac 100644 (file)
--- a/arch/arm/include/debug/vf.S
+++ b/arch/arm/include/debug/vf.S
@@ -29,5 +29,8 @@
        beq     1001b                   @ wait until transmit done
        .endm
 
-       .macro  waituart,rd,rx
+       .macro  waituartcts,rd,rx
+       .endm
+
+       .macro  waituarttxrdy,rd,rx
        .endm

diff --git a/arch/arm/include/debug/vt8500.S b/arch/arm/include/debug/vt8500.S
index 8dc1df2d91b859926978cb9313b30fa4235764c9..d01094fdbc8c8475798dc8e9492d7dbb99db2d48 100644 (file)
--- a/arch/arm/include/debug/vt8500.S
+++ b/arch/arm/include/debug/vt8500.S
@@ -28,7 +28,10 @@
        bne     1001b
        .endm
 
-       .macro  waituart,rd,rx
+       .macro  waituartcts,rd,rx
+       .endm
+
+       .macro  waituarttxrdy,rd,rx
        .endm
 
 #endif

diff --git a/arch/arm/include/debug/zynq.S b/arch/arm/include/debug/zynq.S
index 58d77c972fd680684a2e0f1f8ac40bd19e0d221d..5d42cc35ecf3dd98dd20c81df59bf7a487dd74c4 100644 (file)
--- a/arch/arm/include/debug/zynq.S
+++ b/arch/arm/include/debug/zynq.S
@@ -33,7 +33,10 @@
                strb    \rd, [\rx, #UART_FIFO_OFFSET]   @ TXDATA
                .endm
 
-               .macro  waituart,rd,rx
+               .macro  waituartcts,rd,rx
+               .endm
+
+               .macro  waituarttxrdy,rd,rx
 1001:          ldr     \rd, [\rx, #UART_SR_OFFSET]
 ARM_BE8(       rev     \rd, \rd )
                tst     \rd, #UART_SR_TXEMPTY

diff --git a/arch/arm/kernel/debug.S b/arch/arm/kernel/debug.S
index e112072b579d424c3dfcaad914cc8c576b9590c8..e7c87522c1766d7cf50a8ce55bf6f313daf40a92 100644 (file)
--- a/arch/arm/kernel/debug.S
+++ b/arch/arm/kernel/debug.S
@@ -89,11 +89,13 @@ ENTRY(printascii)
 2:             teq     r1, #'\n'
                bne     3f
                mov     r1, #'\r'
-               waituart r2, r3
+               waituartcts r2, r3
+               waituarttxrdy r2, r3
                senduart r1, r3
                busyuart r2, r3
                mov     r1, #'\n'
-3:             waituart r2, r3
+3:             waituartcts r2, r3
+               waituarttxrdy r2, r3
                senduart r1, r3
                busyuart r2, r3
                b       1b