ARM: dts: rockchip: Fix timer clocks for RK3128

Currently the Rockchip timer source clocks are set to xin24 for no obvious
reason and the actual timer clocks (SCLK_TIMER*) will get disabled during
boot process as they have no user. That will make the SoC stuck as no timer
source exists.

Fixes: a0201bff6259 ("ARM: dts: rockchip: add rk3128 soc dtsi")
Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20230829203721.281455-12-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index 9125bf22e971c2079479b63406dc673bb016e992..88a4b0d6d928d4c2e0636a2a026bfec645129338 100644 (file)
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -234,7 +234,7 @@
                compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
                reg = <0x20044000 0x20>;
                interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru PCLK_TIMER>, <&xin24m>;
+               clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER0>;
                clock-names = "pclk", "timer";
        };
 
@@ -242,7 +242,7 @@
                compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
                reg = <0x20044020 0x20>;
                interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru PCLK_TIMER>, <&xin24m>;
+               clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER1>;
                clock-names = "pclk", "timer";
        };
 
@@ -250,7 +250,7 @@
                compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
                reg = <0x20044040 0x20>;
                interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru PCLK_TIMER>, <&xin24m>;
+               clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER2>;
                clock-names = "pclk", "timer";
        };
 
@@ -258,7 +258,7 @@
                compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
                reg = <0x20044060 0x20>;
                interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru PCLK_TIMER>, <&xin24m>;
+               clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER3>;
                clock-names = "pclk", "timer";
        };
 
@@ -266,7 +266,7 @@
                compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
                reg = <0x20044080 0x20>;
                interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru PCLK_TIMER>, <&xin24m>;
+               clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER4>;
                clock-names = "pclk", "timer";
        };
 
@@ -274,7 +274,7 @@
                compatible = "rockchip,rk3128-timer", "rockchip,rk3288-timer";
                reg = <0x200440a0 0x20>;
                interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
-               clocks = <&cru PCLK_TIMER>, <&xin24m>;
+               clocks = <&cru PCLK_TIMER>, <&cru SCLK_TIMER5>;
                clock-names = "pclk", "timer";
        };