drm/amdgpu: Default disable GDS for compute+gfx

Units in the GDS block default to allowing all VMIDs access to all
entries. Disable shader access to the GDS, GWS, and OA blocks from all
compute and gfx VMIDs by default. For compute, HWS firmware will set
up the access bits for the appropriate VMID when a compute queue
requires access to these blocks.
The driver will handle enabling access on-demand for graphics VMIDs.

Leaving VMID0 with full access because otherwise HWS cannot save or
restore values during task switch.

v2: Fixed code and comment styling.

Signed-off-by: Joseph Greathouse <Joseph.Greathouse@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 98d6cb9e95438711c2ffbdd2363d5dbdcc157006..ef9f552b70013afa1cde41341eba3c0556c1d6b5 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -1516,17 +1516,27 @@ static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
        }
        nv_grbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+}
 
-       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
-          acccess. These should be enabled by FW for target VMIDs. */
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
-               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
-               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
-               WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
-               WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
+{
+       int vmid;
+
+       /*
+        * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
+        * access. Compute VMIDs should be enabled by FW for target VMIDs,
+        * the driver can enable them for graphics. VMID0 should maintain
+        * access so that HWS firmware can save/restore entries.
+        */
+       for (vmid = 1; vmid < 16; vmid++) {
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
        }
 }
 
+
 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
 {
        int i, j, k;
@@ -1629,6 +1639,7 @@ static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 
        gfx_v10_0_init_compute_vmid(adev);
+       gfx_v10_0_init_gds_vmid(adev);
 
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 21187275dfd37e496db7de2de3f21f2518a606f9..53eee129b168132ed5914144e17ee3f71a9ec6cf 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -1879,14 +1879,23 @@ static void gfx_v7_0_init_compute_vmid(struct amdgpu_device *adev)
        }
        cik_srbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+}
 
-       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
-          acccess. These should be enabled by FW for target VMIDs. */
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
-               WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
-               WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
-               WREG32(amdgpu_gds_reg_offset[i].gws, 0);
-               WREG32(amdgpu_gds_reg_offset[i].oa, 0);
+static void gfx_v7_0_init_gds_vmid(struct amdgpu_device *adev)
+{
+       int vmid;
+
+       /*
+        * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
+        * access. Compute VMIDs should be enabled by FW for target VMIDs,
+        * the driver can enable them for graphics. VMID0 should maintain
+        * access so that HWS firmware can save/restore entries.
+        */
+       for (vmid = 1; vmid < 16; vmid++) {
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
        }
 }
 
@@ -1968,6 +1977,7 @@ static void gfx_v7_0_constants_init(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 
        gfx_v7_0_init_compute_vmid(adev);
+       gfx_v7_0_init_gds_vmid(adev);
 
        WREG32(mmSX_DEBUG_1, 0x20);
 

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 751567f78567357c0099cf426c550fe7d9d72b3f..249526317f81a9a101cac8bd5b70a74c157b170b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -3706,14 +3706,23 @@ static void gfx_v8_0_init_compute_vmid(struct amdgpu_device *adev)
        }
        vi_srbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+}
 
-       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
-          acccess. These should be enabled by FW for target VMIDs. */
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
-               WREG32(amdgpu_gds_reg_offset[i].mem_base, 0);
-               WREG32(amdgpu_gds_reg_offset[i].mem_size, 0);
-               WREG32(amdgpu_gds_reg_offset[i].gws, 0);
-               WREG32(amdgpu_gds_reg_offset[i].oa, 0);
+static void gfx_v8_0_init_gds_vmid(struct amdgpu_device *adev)
+{
+       int vmid;
+
+       /*
+        * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
+        * access. Compute VMIDs should be enabled by FW for target VMIDs,
+        * the driver can enable them for graphics. VMID0 should maintain
+        * access so that HWS firmware can save/restore entries.
+        */
+       for (vmid = 1; vmid < 16; vmid++) {
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_base, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].mem_size, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].gws, 0);
+               WREG32(amdgpu_gds_reg_offset[vmid].oa, 0);
        }
 }
 
@@ -3783,6 +3792,7 @@ static void gfx_v8_0_constants_init(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 
        gfx_v8_0_init_compute_vmid(adev);
+       gfx_v8_0_init_gds_vmid(adev);
 
        mutex_lock(&adev->grbm_idx_mutex);
        /*

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index f0a7f85990bc0449878f36869e7e295717829047..65be73eb02d4b2a0f67095c9302b5c7fadb3f38a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -2029,14 +2029,23 @@ static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
        }
        soc15_grbm_select(adev, 0, 0, 0, 0);
        mutex_unlock(&adev->srbm_mutex);
+}
 
-       /* Initialize all compute VMIDs to have no GDS, GWS, or OA
-          acccess. These should be enabled by FW for target VMIDs. */
-       for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
-               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
-               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
-               WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
-               WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
+static void gfx_v9_0_init_gds_vmid(struct amdgpu_device *adev)
+{
+       int vmid;
+
+       /*
+        * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
+        * access. Compute VMIDs should be enabled by FW for target VMIDs,
+        * the driver can enable them for graphics. VMID0 should maintain
+        * access so that HWS firmware can save/restore entries.
+        */
+       for (vmid = 1; vmid < 16; vmid++) {
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
+               WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
        }
 }
 
@@ -2084,6 +2093,7 @@ static void gfx_v9_0_constants_init(struct amdgpu_device *adev)
        mutex_unlock(&adev->srbm_mutex);
 
        gfx_v9_0_init_compute_vmid(adev);
+       gfx_v9_0_init_gds_vmid(adev);
 }
 
 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)