struct uic *uic = irq_desc_get_handler_data(desc);
        u32 msr;
        int src;
-       int subvirq;
 
        raw_spin_lock(&desc->lock);
        if (irqd_is_level_type(idata))
 
        src = 32 - ffs(msr);
 
-       subvirq = irq_linear_revmap(uic->irqhost, src);
-       generic_handle_irq(subvirq);
+       generic_handle_domain_irq(uic->irqhost, src);
 
 uic_irq_ret:
        raw_spin_lock(&desc->lock);
 
        .irq_unmask = cpld_unmask_irq,
 };
 
-static int
+static unsigned int
 cpld_pic_get_irq(int offset, u8 ignore, u8 __iomem *statusp,
                            u8 __iomem *maskp)
 {
-       int cpld_irq;
        u8 status = in_8(statusp);
        u8 mask = in_8(maskp);
 
        status |= (ignore | mask);
 
        if (status == 0xff)
-               return 0;
-
-       cpld_irq = ffz(status) + offset;
+               return ~0;
 
-       return irq_linear_revmap(cpld_pic_host, cpld_irq);
+       return ffz(status) + offset;
 }
 
 static void cpld_pic_cascade(struct irq_desc *desc)
 {
-       unsigned int irq;
+       unsigned int hwirq;
 
-       irq = cpld_pic_get_irq(0, PCI_IGNORE, &cpld_regs->pci_status,
+       hwirq = cpld_pic_get_irq(0, PCI_IGNORE, &cpld_regs->pci_status,
                &cpld_regs->pci_mask);
-       if (irq) {
-               generic_handle_irq(irq);
+       if (hwirq != ~0) {
+               generic_handle_domain_irq(cpld_pic_host, hwirq);
                return;
        }
 
-       irq = cpld_pic_get_irq(8, MISC_IGNORE, &cpld_regs->misc_status,
+       hwirq = cpld_pic_get_irq(8, MISC_IGNORE, &cpld_regs->misc_status,
                &cpld_regs->misc_mask);
-       if (irq) {
-               generic_handle_irq(irq);
+       if (hwirq != ~0) {
+               generic_handle_domain_irq(cpld_pic_host, hwirq);
                return;
        }
 }
 
 static void media5200_irq_cascade(struct irq_desc *desc)
 {
        struct irq_chip *chip = irq_desc_get_chip(desc);
-       int sub_virq, val;
+       int val;
        u32 status, enable;
 
        /* Mask off the cascaded IRQ */
        enable = in_be32(media5200_irq.regs + MEDIA5200_IRQ_STATUS);
        val = ffs((status & enable) >> MEDIA5200_IRQ_SHIFT);
        if (val) {
-               sub_virq = irq_linear_revmap(media5200_irq.irqhost, val - 1);
-               /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i subvirq=%i\n",
-                *          __func__, virq, status, enable, val - 1, sub_virq);
+               generic_handle_domain_irq(media5200_irq.irqhost, val - 1);
+               /* pr_debug("%s: virq=%i s=%.8x e=%.8x hwirq=%i\n",
+                *          __func__, virq, status, enable, val - 1);
                 */
-               generic_handle_irq(sub_virq);
        }
 
        /* Processing done; can reenable the cascade now */
 
 static void mpc52xx_gpt_irq_cascade(struct irq_desc *desc)
 {
        struct mpc52xx_gpt_priv *gpt = irq_desc_get_handler_data(desc);
-       int sub_virq;
        u32 status;
 
        status = in_be32(&gpt->regs->status) & MPC52xx_GPT_STATUS_IRQMASK;
-       if (status) {
-               sub_virq = irq_linear_revmap(gpt->irqhost, 0);
-               generic_handle_irq(sub_virq);
-       }
+       if (status)
+               generic_handle_domain_irq(gpt->irqhost, 0);
 }
 
 static int mpc52xx_gpt_irq_map(struct irq_domain *h, unsigned int virq,
 
                        break;
 
                for (bit = 0; pend != 0; ++bit, pend <<= 1) {
-                       if (pend & 0x80000000) {
-                               int virq = irq_linear_revmap(priv->host, bit);
-                               generic_handle_irq(virq);
-                       }
+                       if (pend & 0x80000000)
+                               generic_handle_domain_irq(priv->host, bit);
                }
        }
 }
 
                        out_be64(&node_iic->iic_is, ack);
                /* handle them */
                for (cascade = 63; cascade >= 0; cascade--)
-                       if (bits & (0x8000000000000000UL >> cascade)) {
-                               unsigned int cirq =
-                                       irq_linear_revmap(iic_host,
+                       if (bits & (0x8000000000000000UL >> cascade))
+                               generic_handle_domain_irq(iic_host,
                                                          base | cascade);
-                               if (cirq)
-                                       generic_handle_irq(cirq);
-                       }
                /* post-ack level interrupts */
                ack = bits & ~IIC_ISR_EDGE_MASK;
                if (ack)
 
 {
        struct irq_chip *chip = irq_desc_get_chip(desc);
        struct spider_pic *pic = irq_desc_get_handler_data(desc);
-       unsigned int cs, virq;
+       unsigned int cs;
 
        cs = in_be32(pic->regs + TIR_CS) >> 24;
-       if (cs == SPIDER_IRQ_INVALID)
-               virq = 0;
-       else
-               virq = irq_linear_revmap(pic->host, cs);
-
-       if (virq)
-               generic_handle_irq(virq);
+       if (cs != SPIDER_IRQ_INVALID)
+               generic_handle_domain_irq(pic->host, cs);
 
        chip->irq_eoi(&desc->irq_data);
 }
 
 static unsigned int __hlwd_pic_get_irq(struct irq_domain *h)
 {
        void __iomem *io_base = h->host_data;
-       int irq;
        u32 irq_status;
 
        irq_status = in_be32(io_base + HW_BROADWAY_ICR) &
        if (irq_status == 0)
                return 0;       /* no more IRQs pending */
 
-       irq = __ffs(irq_status);
-       return irq_linear_revmap(h, irq);
+       return __ffs(irq_status);
 }
 
 static void hlwd_pic_irq_cascade(struct irq_desc *desc)
 {
        struct irq_chip *chip = irq_desc_get_chip(desc);
        struct irq_domain *irq_domain = irq_desc_get_handler_data(desc);
-       unsigned int virq;
+       unsigned int hwirq;
 
        raw_spin_lock(&desc->lock);
        chip->irq_mask(&desc->irq_data); /* IRQ_LEVEL */
        raw_spin_unlock(&desc->lock);
 
-       virq = __hlwd_pic_get_irq(irq_domain);
-       if (virq)
-               generic_handle_irq(virq);
+       hwirq = __hlwd_pic_get_irq(irq_domain);
+       if (hwirq)
+               generic_handle_domain_irq(irq_domain, hwirq);
        else
                pr_err("spurious interrupt!\n");
 
 
 unsigned int hlwd_pic_get_irq(void)
 {
-       return __hlwd_pic_get_irq(hlwd_irq_host);
+       unsigned int hwirq = __hlwd_pic_get_irq(hlwd_irq_host);
+       return hwirq ? irq_linear_revmap(hlwd_irq_host, hwirq) : 0;
 }
 
 /*
 
        e = READ_ONCE(last_outstanding_events) & opal_event_irqchip.mask;
 again:
        while (e) {
-               int virq, hwirq;
+               int hwirq;
 
                hwirq = fls64(e) - 1;
                e &= ~BIT_ULL(hwirq);
 
                local_irq_disable();
-               virq = irq_find_mapping(opal_event_irqchip.domain, hwirq);
-               if (virq) {
-                       irq_enter();
-                       generic_handle_irq(virq);
-                       irq_exit();
-               }
+               irq_enter();
+               generic_handle_domain_irq(opal_event_irqchip.domain, hwirq);
+               irq_exit();
                local_irq_enable();
 
                cond_resched();
 
        struct mpic *mpic = (struct mpic *) data;
        u32 eisr, eimr;
        int errint;
-       unsigned int cascade_irq;
 
        eisr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EISR);
        eimr = mpic_fsl_err_read(mpic->err_regs, MPIC_ERR_INT_EIMR);
                return IRQ_NONE;
 
        while (eisr) {
+               int ret;
                errint = __builtin_clz(eisr);
-               cascade_irq = irq_linear_revmap(mpic->irqhost,
-                                mpic->err_int_vecs[errint]);
-               WARN_ON(!cascade_irq);
-               if (cascade_irq) {
-                       generic_handle_irq(cascade_irq);
-               } else {
+               ret = generic_handle_domain_irq(mpic->irqhost,
+                                               mpic->err_int_vecs[errint]);
+               if (WARN_ON(ret)) {
                        eimr |=  1 << (31 - errint);
                        mpic_fsl_err_write(mpic->err_regs, eimr);
                }
 
 
 static irqreturn_t fsl_msi_cascade(int irq, void *data)
 {
-       unsigned int cascade_irq;
        struct fsl_msi *msi_data;
        int msir_index = -1;
        u32 msir_value = 0;
 
        msir_index = cascade_data->index;
 
-       if (msir_index >= NR_MSI_REG_MAX)
-               cascade_irq = 0;
-
        switch (msi_data->feature & FSL_PIC_IP_MASK) {
        case FSL_PIC_IP_MPIC:
                msir_value = fsl_msi_read(msi_data->msi_regs,
        }
 
        while (msir_value) {
+               int err;
                intr_index = ffs(msir_value) - 1;
 
-               cascade_irq = irq_linear_revmap(msi_data->irqhost,
+               err = generic_handle_domain_irq(msi_data->irqhost,
                                msi_hwirq(msi_data, msir_index,
                                          intr_index + have_shift));
-               if (cascade_irq) {
-                       generic_handle_irq(cascade_irq);
+               if (!err)
                        ret = IRQ_HANDLED;
-               }
+
                have_shift += intr_index + 1;
                msir_value = msir_value >> (intr_index + 1);
        }