RDMA/hns: Add max_ah and cq moderation capacities in query_device()
authorChengchang Tang <tangchengchang@huawei.com>
Fri, 12 Apr 2024 09:16:09 +0000 (17:16 +0800)
committerLeon Romanovsky <leon@kernel.org>
Tue, 16 Apr 2024 12:06:47 +0000 (15:06 +0300)
Add max_ah and cq moderation capacities to hns_roce_query_device().

Fixes: 9a4435375cd1 ("IB/hns: Add driver files for hns RoCE driver")
Signed-off-by: Chengchang Tang <tangchengchang@huawei.com>
Signed-off-by: Junxian Huang <huangjunxian6@hisilicon.com>
Link: https://lore.kernel.org/r/20240412091616.370789-4-huangjunxian6@hisilicon.com
Signed-off-by: Leon Romanovsky <leon@kernel.org>
drivers/infiniband/hw/hns/hns_roce_device.h
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
drivers/infiniband/hw/hns/hns_roce_hw_v2.h
drivers/infiniband/hw/hns/hns_roce_main.c

index 37888f78849d41b75a5e01895a38771670457973..ff0b3f68ee3a4008b69cbfc44ebf43994682ea77 100644 (file)
 #define CQ_BANKID_SHIFT 2
 #define CQ_BANKID_MASK GENMASK(1, 0)
 
+#define HNS_ROCE_MAX_CQ_COUNT 0xFFFF
+#define HNS_ROCE_MAX_CQ_PERIOD 0xFFFF
+
 enum {
        SERV_TYPE_RC,
        SERV_TYPE_UC,
index e3f87090bad094cbecbc1ebd1633b097724a91ad..2a97a81ae19fcffdaef39da2d64a08b4fe1c5588 100644 (file)
@@ -5848,7 +5848,7 @@ static int hns_roce_v2_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period)
                        dev_info(hr_dev->dev,
                                 "cq_period(%u) reached the upper limit, adjusted to 65.\n",
                                 cq_period);
-                       cq_period = HNS_ROCE_MAX_CQ_PERIOD;
+                       cq_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08;
                }
                cq_period *= HNS_ROCE_CLOCK_ADJUST;
        }
index 4bac34f6bbe8a8a8ad374ecd9e2cd0f4340b3638..def1d15a03c7ea159bcf835b8cc0043b58d1c1c9 100644 (file)
@@ -1347,7 +1347,7 @@ struct fmea_ram_ecc {
 
 /* only for RNR timeout issue of HIP08 */
 #define HNS_ROCE_CLOCK_ADJUST 1000
-#define HNS_ROCE_MAX_CQ_PERIOD 65
+#define HNS_ROCE_MAX_CQ_PERIOD_HIP08 65
 #define HNS_ROCE_MAX_EQ_PERIOD 65
 #define HNS_ROCE_RNR_TIMER_10NS 1
 #define HNS_ROCE_1US_CFG 999
index 1dc60c2b2b7ab841266a4e25da2af3a4ce8218b9..4d94fcb8685ab0f4b80a9d9bda7a504248a8f883 100644 (file)
@@ -40,6 +40,7 @@
 #include "hns_roce_common.h"
 #include "hns_roce_device.h"
 #include "hns_roce_hem.h"
+#include "hns_roce_hw_v2.h"
 
 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u32 port,
                            const u8 *addr)
@@ -192,6 +193,12 @@ static int hns_roce_query_device(struct ib_device *ib_dev,
                            IB_ATOMIC_HCA : IB_ATOMIC_NONE;
        props->max_pkeys = 1;
        props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
+       props->max_ah = INT_MAX;
+       props->cq_caps.max_cq_moderation_period = HNS_ROCE_MAX_CQ_PERIOD;
+       props->cq_caps.max_cq_moderation_count = HNS_ROCE_MAX_CQ_COUNT;
+       if (hr_dev->pci_dev->revision == PCI_REVISION_ID_HIP08)
+               props->cq_caps.max_cq_moderation_period = HNS_ROCE_MAX_CQ_PERIOD_HIP08;
+
        if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_SRQ) {
                props->max_srq = hr_dev->caps.num_srqs;
                props->max_srq_wr = hr_dev->caps.max_srq_wrs;