drm/msm/dpu: always use MSM_DP/DSI_CONTROLLER_n

In several catalog entries we did not use existing MSM_DP_CONTROLLER_n
constants. Fill them in. Also use freshly defined MSM_DSI_CONTROLLER_n
for DSI interfaces.

Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Tested-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/545353/
Link: https://lore.kernel.org/r/20230704022136.130522-3-dmitry.baryshkov@linaro.org

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
index 7d0d0e74c3b0807bac2516015647b731d275635a..be0514bf27ec72b92b1c46f4f637980cf5731f57 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h
@@ -139,13 +139,13 @@ static const struct dpu_dspp_cfg msm8998_dspp[] = {
 };
 
 static const struct dpu_intf_cfg msm8998_intf[] = {
-       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 21, INTF_SDM845_MASK,
+       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 21, INTF_SDM845_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 21, INTF_SDM845_MASK,
+       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 21, INTF_SDM845_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
-       INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 21, INTF_SDM845_MASK,
+       INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 21, INTF_SDM845_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
        INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_HDMI, 0, 21, INTF_SDM845_MASK,

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
index 18e27f7550e66fda3391519e0b13ea13ff24dd38..8944405334556289b956881d9b4a8fe485cbf3d5 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h
@@ -143,16 +143,16 @@ static const struct dpu_dsc_cfg sdm845_dsc[] = {
 };
 
 static const struct dpu_intf_cfg sdm845_intf[] = {
-       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SDM845_MASK,
+       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SDM845_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, 0, 24, INTF_SDM845_MASK,
+       INTF_BLK("intf_1", INTF_1, 0x6a800, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SDM845_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27)),
-       INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, 1, 24, INTF_SDM845_MASK,
+       INTF_BLK("intf_2", INTF_2, 0x6b000, 0x280, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SDM845_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29)),
-       INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SDM845_MASK,
+       INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SDM845_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
 };

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
index a654ba8226cd2432fdec1b4240f3213d5566049c..9a5ce15df018bc3ec42ee589e7304ef187b8f0f1 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_0_sm8150.h
@@ -162,18 +162,18 @@ static const struct dpu_dsc_cfg sm8150_dsc[] = {
 };
 
 static const struct dpu_intf_cfg sm8150_intf[] = {
-       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                        DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
-       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
                        DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
-       INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,
+       INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
 };

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
index 6dd24bd39a68a90b3b44d3ab51f3e5c5e334b57f..2d8f0640162e1f63db46517653a95fda4c6b9441 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_5_1_sc8180x.h
@@ -166,11 +166,11 @@ static const struct dpu_intf_cfg sc8180x_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                        DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
-       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, 1, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2bc, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
                        DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
index 6a6d37c1dededd1f7a690d67cef80a627a3073d9..2aa65b82c55624d56f94f5fd882e4107599e1e63 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_0_sm8250.h
@@ -163,18 +163,18 @@ static const struct dpu_dsc_cfg sm8250_dsc[] = {
 };
 
 static const struct dpu_intf_cfg sm8250_intf[] = {
-       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                        DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),
-       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, 1, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x6b000, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
                        DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2)),
-       INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, 1, 24, INTF_SC7180_MASK,
+       INTF_BLK("intf_3", INTF_3, 0x6b800, 0x280, INTF_DP, MSM_DP_CONTROLLER_1, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31)),
 };

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
index a3124661cb65fd2df28110bbdded327406cbdfe5..74d10dff545c9ed719f2812ef576afe3bfcf3bc7 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_2_sc7180.h
@@ -92,7 +92,7 @@ static const struct dpu_intf_cfg sc7180_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                        DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
index 04a0dbf96e17982f93d239c2c7eca2fd007c228b..b17cc8baf678b394cf1758d4000f6591ad960a6a 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_3_sm6115.h
@@ -66,7 +66,7 @@ static const struct dpu_pingpong_cfg sm6115_pp[] = {
 };
 
 static const struct dpu_intf_cfg sm6115_intf[] = {
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                        DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
index 3262a5232b5a35015d6b346c6637914db71ae09b..550a660d0f34497209db8e036f9d43c76af3abb3 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_4_sm6350.h
@@ -102,10 +102,10 @@ static const struct dpu_dsc_cfg sm6350_dsc[] = {
 };
 
 static const struct dpu_intf_cfg sm6350_intf[] = {
-       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, 0, 35, INTF_SC7180_MASK,
+       INTF_BLK("intf_0", INTF_0, 0x6a000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 35, INTF_SC7180_MASK,
                DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 35, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 35, INTF_SC7180_MASK,
                DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
index 06cf48b55f989ce4cfd40a40ada40cb094ae8eb5..ade9c4a5ec4e889f5456735fd38c516aa61760fc 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_5_qcm2290.h
@@ -63,7 +63,7 @@ static const struct dpu_pingpong_cfg qcm2290_pp[] = {
 };
 
 static const struct dpu_intf_cfg qcm2290_intf[] = {
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                        DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
index a01c7ea43c3399f2516678292b4e923bb93b6a8b..664e45c31a123ff063753c724ea09dfaf306fbf5 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_6_9_sm6375.h
@@ -71,7 +71,7 @@ static const struct dpu_dsc_cfg sm6375_dsc[] = {
 };
 
 static const struct dpu_intf_cfg sm6375_intf[] = {
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, 0, 24, INTF_SC7180_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x6a800, 0x2c0, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7180_MASK,
                DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2)),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
index 8f3bf7964ba0413b2c158943970d3b075180def4..c151f8b9f667f8ce6af7af41171257bbb7181b53 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_0_sm8350.h
@@ -169,11 +169,11 @@ static const struct dpu_intf_cfg sm8350_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                        DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
-       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
                        DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
index 1624e5035a2c35fd874ba6e67a62b1e5f56f7393..b702bab35707c295a8be7820b63f8a7cf895f15d 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h
@@ -116,7 +116,7 @@ static const struct dpu_intf_cfg sc7280_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x2c4, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                        DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
index 1362552027fbc61226dfccd5e6cd2f78becf1168..d3fa49fe93a686984f4b26f33d54b0fc5703db83 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_0_sc8280xp.h
@@ -161,11 +161,11 @@ static const struct dpu_intf_cfg sc8280xp_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                        DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
-       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
                        DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
index c368a216933a4988765933bfaea8944ff8cd5adc..d33fdcb7307f16c800259c87e980f7d99cd796b6 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_8_1_sm8450.h
@@ -177,11 +177,11 @@ static const struct dpu_intf_cfg sm8450_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                        DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
-       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
                        DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),

diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
index 22096c1a828779d5bae711a36cbddc5480d27086..95d3f6479fdaec378ffc18032f1a90729a5fe249 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_0_sm8550.h
@@ -181,11 +181,11 @@ static const struct dpu_intf_cfg sm8550_intf[] = {
        INTF_BLK("intf_0", INTF_0, 0x34000, 0x280, INTF_DP, MSM_DP_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25)),
-       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, 0, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_1", INTF_1, 0x35000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_0, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27),
                        DPU_IRQ_IDX(MDP_INTF1_7xxx_TEAR_INTR, 2)),
-       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, 1, 24, INTF_SC7280_MASK,
+       INTF_BLK_DSI_TE("intf_2", INTF_2, 0x36000, 0x300, INTF_DSI, MSM_DSI_CONTROLLER_1, 24, INTF_SC7280_MASK,
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28),
                        DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29),
                        DPU_IRQ_IDX(MDP_INTF2_7xxx_TEAR_INTR, 2)),