arm64/sysreg: Add _EL1 into ID_AA64MMFR0_EL1 definition names

Normally we include the full register name in the defines for fields within
registers but this has not been followed for ID registers. In preparation
for automatic generation of defines add the _EL1s into the defines for
ID_AA64MMFR0_EL1 to follow the convention. No functional changes.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Kristina Martsenko <kristina.martsenko@arm.com>
Link: https://lore.kernel.org/r/20220905225425.1871461-5-broonie@kernel.org
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/assembler.h b/arch/arm64/include/asm/assembler.h
index 5846145be523c64c4e5c5be4e57cd9e9c2104ad0..a6e7061d84e79bafa706cc2c7543f1cc7f6e8357 100644 (file)
--- a/arch/arm64/include/asm/assembler.h
+++ b/arch/arm64/include/asm/assembler.h
@@ -384,8 +384,8 @@ alternative_cb_end
        .macro  tcr_compute_pa_size, tcr, pos, tmp0, tmp1
        mrs     \tmp0, ID_AA64MMFR0_EL1
        // Narrow PARange to fit the PS field in TCR_ELx
-       ubfx    \tmp0, \tmp0, #ID_AA64MMFR0_PARANGE_SHIFT, #3
-       mov     \tmp1, #ID_AA64MMFR0_PARANGE_MAX
+       ubfx    \tmp0, \tmp0, #ID_AA64MMFR0_EL1_PARANGE_SHIFT, #3
+       mov     \tmp1, #ID_AA64MMFR0_EL1_PARANGE_MAX
        cmp     \tmp0, \tmp1
        csel    \tmp0, \tmp1, \tmp0, hi
        bfi     \tcr, \tmp0, \pos, #3

diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h
index fd7d75a275f6c1c8c66110312d457b26501d9d5e..96ccf823f46e5997c9e83a9b118b54362392cc13 100644 (file)
--- a/arch/arm64/include/asm/cpufeature.h
+++ b/arch/arm64/include/asm/cpufeature.h
@@ -597,8 +597,8 @@ static inline s64 arm64_ftr_value(const struct arm64_ftr_bits *ftrp, u64 val)
 
 static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
 {
-       return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
-               cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
+       return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGENDEL_SHIFT) == 0x1 ||
+               cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT) == 0x1;
 }
 
 static inline bool id_aa64pfr0_32bit_el1(u64 pfr0)
@@ -694,10 +694,10 @@ static inline bool system_supports_4kb_granule(void)
 
        mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
        val = cpuid_feature_extract_unsigned_field(mmfr0,
-                                               ID_AA64MMFR0_TGRAN4_SHIFT);
+                                               ID_AA64MMFR0_EL1_TGRAN4_SHIFT);
 
-       return (val >= ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN) &&
-              (val <= ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX);
+       return (val >= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN) &&
+              (val <= ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX);
 }
 
 static inline bool system_supports_64kb_granule(void)
@@ -707,10 +707,10 @@ static inline bool system_supports_64kb_granule(void)
 
        mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
        val = cpuid_feature_extract_unsigned_field(mmfr0,
-                                               ID_AA64MMFR0_TGRAN64_SHIFT);
+                                               ID_AA64MMFR0_EL1_TGRAN64_SHIFT);
 
-       return (val >= ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN) &&
-              (val <= ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX);
+       return (val >= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN) &&
+              (val <= ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX);
 }
 
 static inline bool system_supports_16kb_granule(void)
@@ -720,10 +720,10 @@ static inline bool system_supports_16kb_granule(void)
 
        mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
        val = cpuid_feature_extract_unsigned_field(mmfr0,
-                                               ID_AA64MMFR0_TGRAN16_SHIFT);
+                                               ID_AA64MMFR0_EL1_TGRAN16_SHIFT);
 
-       return (val >= ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN) &&
-              (val <= ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX);
+       return (val >= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN) &&
+              (val <= ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX);
 }
 
 static inline bool system_supports_mixed_endian_el0(void)
@@ -738,7 +738,7 @@ static inline bool system_supports_mixed_endian(void)
 
        mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
        val = cpuid_feature_extract_unsigned_field(mmfr0,
-                                               ID_AA64MMFR0_BIGENDEL_SHIFT);
+                                               ID_AA64MMFR0_EL1_BIGENDEL_SHIFT);
 
        return val == 0x1;
 }
@@ -840,13 +840,13 @@ extern int do_emulate_mrs(struct pt_regs *regs, u32 sys_reg, u32 rt);
 static inline u32 id_aa64mmfr0_parange_to_phys_shift(int parange)
 {
        switch (parange) {
-       case ID_AA64MMFR0_PARANGE_32: return 32;
-       case ID_AA64MMFR0_PARANGE_36: return 36;
-       case ID_AA64MMFR0_PARANGE_40: return 40;
-       case ID_AA64MMFR0_PARANGE_42: return 42;
-       case ID_AA64MMFR0_PARANGE_44: return 44;
-       case ID_AA64MMFR0_PARANGE_48: return 48;
-       case ID_AA64MMFR0_PARANGE_52: return 52;
+       case ID_AA64MMFR0_EL1_PARANGE_32: return 32;
+       case ID_AA64MMFR0_EL1_PARANGE_36: return 36;
+       case ID_AA64MMFR0_EL1_PARANGE_40: return 40;
+       case ID_AA64MMFR0_EL1_PARANGE_42: return 42;
+       case ID_AA64MMFR0_EL1_PARANGE_44: return 44;
+       case ID_AA64MMFR0_EL1_PARANGE_48: return 48;
+       case ID_AA64MMFR0_EL1_PARANGE_52: return 52;
        /*
         * A future PE could use a value unknown to the kernel.
         * However, by the "D10.1.4 Principles of the ID scheme

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 2630faa5bc08fc5879cb6595fb39f8fd2d44ab42..faad9e01e52bda117d7fd7c02d0ffa036ebadc66 100644 (file)
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -132,7 +132,7 @@
 /* Disable any fine grained traps */
 .macro __init_el2_fgt
        mrs     x1, id_aa64mmfr0_el1
-       ubfx    x1, x1, #ID_AA64MMFR0_FGT_SHIFT, #4
+       ubfx    x1, x1, #ID_AA64MMFR0_EL1_FGT_SHIFT, #4
        cbz     x1, .Lskip_fgt_\@
 
        mov     x0, xzr

diff --git a/arch/arm64/include/asm/kvm_pgtable.h b/arch/arm64/include/asm/kvm_pgtable.h
index 9f339dffbc1a7e12c29df923badbb66dde48f60f..1b098bd4cd37826539b899fb77e31aff87827be6 100644 (file)
--- a/arch/arm64/include/asm/kvm_pgtable.h
+++ b/arch/arm64/include/asm/kvm_pgtable.h
@@ -16,9 +16,9 @@
 static inline u64 kvm_get_parange(u64 mmfr0)
 {
        u64 parange = cpuid_feature_extract_unsigned_field(mmfr0,
-                               ID_AA64MMFR0_PARANGE_SHIFT);
-       if (parange > ID_AA64MMFR0_PARANGE_MAX)
-               parange = ID_AA64MMFR0_PARANGE_MAX;
+                               ID_AA64MMFR0_EL1_PARANGE_SHIFT);
+       if (parange > ID_AA64MMFR0_EL1_PARANGE_MAX)
+               parange = ID_AA64MMFR0_EL1_PARANGE_MAX;
 
        return parange;
 }

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 62376ef4a4f1f3c85eeef5dbae5445b1cbcc68e3..f9af77ab5f98d597efbe5716a70091e893f0766f 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -733,53 +733,53 @@
 #define ID_AA64PFR1_MTE_ASYMM          0x3
 
 /* id_aa64mmfr0 */
-#define ID_AA64MMFR0_ECV_SHIFT         60
-#define ID_AA64MMFR0_FGT_SHIFT         56
-#define ID_AA64MMFR0_EXS_SHIFT         44
-#define ID_AA64MMFR0_TGRAN4_2_SHIFT    40
-#define ID_AA64MMFR0_TGRAN64_2_SHIFT   36
-#define ID_AA64MMFR0_TGRAN16_2_SHIFT   32
-#define ID_AA64MMFR0_TGRAN4_SHIFT      28
-#define ID_AA64MMFR0_TGRAN64_SHIFT     24
-#define ID_AA64MMFR0_TGRAN16_SHIFT     20
-#define ID_AA64MMFR0_BIGENDEL0_SHIFT   16
-#define ID_AA64MMFR0_SNSMEM_SHIFT      12
-#define ID_AA64MMFR0_BIGENDEL_SHIFT    8
-#define ID_AA64MMFR0_ASID_SHIFT                4
-#define ID_AA64MMFR0_PARANGE_SHIFT     0
-
-#define ID_AA64MMFR0_ASID_8            0x0
-#define ID_AA64MMFR0_ASID_16           0x2
-
-#define ID_AA64MMFR0_TGRAN4_NI                 0xf
-#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN      0x0
-#define ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX      0x7
-#define ID_AA64MMFR0_TGRAN64_NI                        0xf
-#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN     0x0
-#define ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX     0x7
-#define ID_AA64MMFR0_TGRAN16_NI                        0x0
-#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN     0x1
-#define ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX     0xf
-
-#define ID_AA64MMFR0_PARANGE_32                0x0
-#define ID_AA64MMFR0_PARANGE_36                0x1
-#define ID_AA64MMFR0_PARANGE_40                0x2
-#define ID_AA64MMFR0_PARANGE_42                0x3
-#define ID_AA64MMFR0_PARANGE_44                0x4
-#define ID_AA64MMFR0_PARANGE_48                0x5
-#define ID_AA64MMFR0_PARANGE_52                0x6
+#define ID_AA64MMFR0_EL1_ECV_SHIFT             60
+#define ID_AA64MMFR0_EL1_FGT_SHIFT             56
+#define ID_AA64MMFR0_EL1_EXS_SHIFT             44
+#define ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT                40
+#define ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT       36
+#define ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT       32
+#define ID_AA64MMFR0_EL1_TGRAN4_SHIFT          28
+#define ID_AA64MMFR0_EL1_TGRAN64_SHIFT         24
+#define ID_AA64MMFR0_EL1_TGRAN16_SHIFT         20
+#define ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT       16
+#define ID_AA64MMFR0_EL1_SNSMEM_SHIFT          12
+#define ID_AA64MMFR0_EL1_BIGENDEL_SHIFT                8
+#define ID_AA64MMFR0_EL1_ASID_SHIFT            4
+#define ID_AA64MMFR0_EL1_PARANGE_SHIFT         0
+
+#define ID_AA64MMFR0_EL1_ASID_8                        0x0
+#define ID_AA64MMFR0_EL1_ASID_16               0x2
+
+#define ID_AA64MMFR0_EL1_TGRAN4_NI             0xf
+#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN  0x0
+#define ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX  0x7
+#define ID_AA64MMFR0_EL1_TGRAN64_NI            0xf
+#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN 0x0
+#define ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX 0x7
+#define ID_AA64MMFR0_EL1_TGRAN16_NI            0x0
+#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN 0x1
+#define ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX 0xf
+
+#define ID_AA64MMFR0_EL1_PARANGE_32            0x0
+#define ID_AA64MMFR0_EL1_PARANGE_36            0x1
+#define ID_AA64MMFR0_EL1_PARANGE_40            0x2
+#define ID_AA64MMFR0_EL1_PARANGE_42            0x3
+#define ID_AA64MMFR0_EL1_PARANGE_44            0x4
+#define ID_AA64MMFR0_EL1_PARANGE_48            0x5
+#define ID_AA64MMFR0_EL1_PARANGE_52            0x6
 
 #define ARM64_MIN_PARANGE_BITS         32
 
-#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT 0x0
-#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE    0x1
-#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN     0x2
-#define ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX     0x7
+#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT     0x0
+#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE                0x1
+#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN         0x2
+#define ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX         0x7
 
 #ifdef CONFIG_ARM64_PA_BITS_52
-#define ID_AA64MMFR0_PARANGE_MAX       ID_AA64MMFR0_PARANGE_52
+#define ID_AA64MMFR0_EL1_PARANGE_MAX   ID_AA64MMFR0_EL1_PARANGE_52
 #else
-#define ID_AA64MMFR0_PARANGE_MAX       ID_AA64MMFR0_PARANGE_48
+#define ID_AA64MMFR0_EL1_PARANGE_MAX   ID_AA64MMFR0_EL1_PARANGE_48
 #endif
 
 /* id_aa64mmfr1 */
@@ -951,20 +951,20 @@
 #define ID_PFR1_PROGMOD_SHIFT          0
 
 #if defined(CONFIG_ARM64_4K_PAGES)
-#define ID_AA64MMFR0_TGRAN_SHIFT               ID_AA64MMFR0_TGRAN4_SHIFT
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN4_SUPPORTED_MIN
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       ID_AA64MMFR0_TGRAN4_SUPPORTED_MAX
-#define ID_AA64MMFR0_TGRAN_2_SHIFT             ID_AA64MMFR0_TGRAN4_2_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SHIFT           ID_AA64MMFR0_EL1_TGRAN4_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN   ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MIN
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX   ID_AA64MMFR0_EL1_TGRAN4_SUPPORTED_MAX
+#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT         ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT
 #elif defined(CONFIG_ARM64_16K_PAGES)
-#define ID_AA64MMFR0_TGRAN_SHIFT               ID_AA64MMFR0_TGRAN16_SHIFT
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN16_SUPPORTED_MIN
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       ID_AA64MMFR0_TGRAN16_SUPPORTED_MAX
-#define ID_AA64MMFR0_TGRAN_2_SHIFT             ID_AA64MMFR0_TGRAN16_2_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SHIFT           ID_AA64MMFR0_EL1_TGRAN16_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN   ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MIN
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX   ID_AA64MMFR0_EL1_TGRAN16_SUPPORTED_MAX
+#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT         ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT
 #elif defined(CONFIG_ARM64_64K_PAGES)
-#define ID_AA64MMFR0_TGRAN_SHIFT               ID_AA64MMFR0_TGRAN64_SHIFT
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MIN       ID_AA64MMFR0_TGRAN64_SUPPORTED_MIN
-#define ID_AA64MMFR0_TGRAN_SUPPORTED_MAX       ID_AA64MMFR0_TGRAN64_SUPPORTED_MAX
-#define ID_AA64MMFR0_TGRAN_2_SHIFT             ID_AA64MMFR0_TGRAN64_2_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SHIFT           ID_AA64MMFR0_EL1_TGRAN64_SHIFT
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN   ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MIN
+#define ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX   ID_AA64MMFR0_EL1_TGRAN64_SUPPORTED_MAX
+#define ID_AA64MMFR0_EL1_TGRAN_2_SHIFT         ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT
 #endif
 
 #define MVFR2_FPMISC_SHIFT             4

diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index af4de817d7123a3608fdcab8b2c1dc42bcdc42aa..3f4512267fe41e540b28b52c16066dc40a3ac43c 100644 (file)
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -316,9 +316,9 @@ static const struct arm64_ftr_bits ftr_id_aa64smfr0[] = {
 };
 
 static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
-       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ECV_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_FGT_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EXS_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_FGT_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_EXS_SHIFT, 4, 0),
        /*
         * Page size not being supported at Stage-2 is not fatal. You
         * just give up KVM if PAGE_SIZE isn't supported there. Go fix
@@ -334,9 +334,9 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
         * fields are inconsistent across vCPUs, then it isn't worth
         * trying to bring KVM up.
         */
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN4_2_SHIFT, 4, 1),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN64_2_SHIFT, 4, 1),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_TGRAN16_2_SHIFT, 4, 1),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN4_2_SHIFT, 4, 1),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN64_2_SHIFT, 4, 1),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_EXACT, ID_AA64MMFR0_EL1_TGRAN16_2_SHIFT, 4, 1),
        /*
         * We already refuse to boot CPUs that don't support our configured
         * page size, so we can only detect mismatches for a page size other
@@ -344,20 +344,20 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr0[] = {
         * exist in the wild so, even though we don't like it, we'll have to go
         * along with it and treat them as non-strict.
         */
-       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN4_SHIFT, 4, ID_AA64MMFR0_TGRAN4_NI),
-       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN64_SHIFT, 4, ID_AA64MMFR0_TGRAN64_NI),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_TGRAN16_SHIFT, 4, ID_AA64MMFR0_TGRAN16_NI),
+       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN4_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN4_NI),
+       S_ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN64_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN64_NI),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_TGRAN16_SHIFT, 4, ID_AA64MMFR0_EL1_TGRAN16_NI),
 
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL0_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL0_SHIFT, 4, 0),
        /* Linux shouldn't care about secure memory */
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_SNSMEM_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_BIGENDEL_SHIFT, 4, 0),
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_ASID_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_SNSMEM_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_BIGENDEL_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_ASID_SHIFT, 4, 0),
        /*
         * Differing PARange is fine as long as all peripherals and memory are mapped
         * within the minimum PARange of all CPUs
         */
-       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_PARANGE_SHIFT, 4, 0),
+       ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR0_EL1_PARANGE_SHIFT, 4, 0),
        ARM64_FTR_END,
 };
 
@@ -2104,7 +2104,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
                .type = ARM64_CPUCAP_SYSTEM_FEATURE,
                .matches = has_cpuid_feature,
                .sys_reg = SYS_ID_AA64MMFR0_EL1,
-               .field_pos = ID_AA64MMFR0_ECV_SHIFT,
+               .field_pos = ID_AA64MMFR0_EL1_ECV_SHIFT,
                .field_width = 4,
                .sign = FTR_UNSIGNED,
                .min_field_value = 1,
@@ -2751,7 +2751,7 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = {
        HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE, CAP_HWCAP, KERNEL_HWCAP_MTE),
        HWCAP_CAP(SYS_ID_AA64PFR1_EL1, ID_AA64PFR1_MTE_SHIFT, 4, FTR_UNSIGNED, ID_AA64PFR1_MTE_ASYMM, CAP_HWCAP, KERNEL_HWCAP_MTE3),
 #endif /* CONFIG_ARM64_MTE */
-       HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
+       HWCAP_CAP(SYS_ID_AA64MMFR0_EL1, ID_AA64MMFR0_EL1_ECV_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_ECV),
        HWCAP_CAP(SYS_ID_AA64MMFR1_EL1, ID_AA64MMFR1_AFP_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_AFP),
        HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_RPRES_SHIFT, 4, FTR_UNSIGNED, 1, CAP_HWCAP, KERNEL_HWCAP_RPRES),
        HWCAP_CAP(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_EL1_WFxT_SHIFT, 4, FTR_UNSIGNED, ID_AA64ISAR2_EL1_WFxT_IMP, CAP_HWCAP, KERNEL_HWCAP_WFXT),
@@ -3102,7 +3102,7 @@ static void verify_hyp_capabilities(void)
 
        /* Verify IPA range */
        parange = cpuid_feature_extract_unsigned_field(mmfr0,
-                               ID_AA64MMFR0_PARANGE_SHIFT);
+                               ID_AA64MMFR0_EL1_PARANGE_SHIFT);
        ipa_max = id_aa64mmfr0_parange_to_phys_shift(parange);
        if (ipa_max < get_kvm_ipa_limit()) {
                pr_crit("CPU%d: IPA range mismatch\n", smp_processor_id());

diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index cefe6a73ee546c26e8971bce4abf4b01f6e5f96d..bffb034d8f730e0881b97032c92a419ba3b8f196 100644 (file)
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -656,10 +656,10 @@ SYM_FUNC_END(__secondary_too_slow)
  */
 SYM_FUNC_START(__enable_mmu)
        mrs     x3, ID_AA64MMFR0_EL1
-       ubfx    x3, x3, #ID_AA64MMFR0_TGRAN_SHIFT, 4
-       cmp     x3, #ID_AA64MMFR0_TGRAN_SUPPORTED_MIN
+       ubfx    x3, x3, #ID_AA64MMFR0_EL1_TGRAN_SHIFT, 4
+       cmp     x3, #ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN
        b.lt    __no_granule_support
-       cmp     x3, #ID_AA64MMFR0_TGRAN_SUPPORTED_MAX
+       cmp     x3, #ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX
        b.gt    __no_granule_support
        phys_to_ttbr x2, x2
        msr     ttbr0_el1, x2                   // load TTBR0

diff --git a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
index fa6e466ed57f60640d5a502aac53517bbad2d592..aac538c34f874fc546eb2d319f48579b9c4f993f 100644 (file)
--- a/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
+++ b/arch/arm64/kvm/hyp/include/nvhe/fixed_config.h
@@ -74,10 +74,10 @@
  * - Non-context synchronizing exception entry and exit
  */
 #define PVM_ID_AA64MMFR0_ALLOW (\
-       ARM64_FEATURE_MASK(ID_AA64MMFR0_BIGENDEL) | \
-       ARM64_FEATURE_MASK(ID_AA64MMFR0_SNSMEM) | \
-       ARM64_FEATURE_MASK(ID_AA64MMFR0_BIGENDEL0) | \
-       ARM64_FEATURE_MASK(ID_AA64MMFR0_EXS) \
+       ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGENDEL) | \
+       ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_SNSMEM) | \
+       ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_BIGENDEL0) | \
+       ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_EXS) \
        )
 
 /*
@@ -86,8 +86,8 @@
  * - 16-bit ASID
  */
 #define PVM_ID_AA64MMFR0_RESTRICT_UNSIGNED (\
-       FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_PARANGE), ID_AA64MMFR0_PARANGE_40) | \
-       FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_ASID), ID_AA64MMFR0_ASID_16) \
+       FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_PARANGE), ID_AA64MMFR0_EL1_PARANGE_40) | \
+       FIELD_PREP(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_ASID), ID_AA64MMFR0_EL1_ASID_16) \
        )
 
 /*

diff --git a/arch/arm64/kvm/hyp/nvhe/pkvm.c b/arch/arm64/kvm/hyp/nvhe/pkvm.c
index 99c8d8b73e70479b74f97e813aca4b21561ef929..823eb4d03956ffb912459017b98623f7ffe19c89 100644 (file)
--- a/arch/arm64/kvm/hyp/nvhe/pkvm.c
+++ b/arch/arm64/kvm/hyp/nvhe/pkvm.c
@@ -128,7 +128,7 @@ static void pvm_init_traps_aa64mmfr0(struct kvm_vcpu *vcpu)
        u64 mdcr_set = 0;
 
        /* Trap Debug Communications Channel registers */
-       if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_FGT), feature_ids))
+       if (!FIELD_GET(ARM64_FEATURE_MASK(ID_AA64MMFR0_EL1_FGT), feature_ids))
                mdcr_set |= MDCR_EL2_TDCC;
 
        vcpu->arch.mdcr_el2 |= mdcr_set;

diff --git a/arch/arm64/kvm/hyp/pgtable.c b/arch/arm64/kvm/hyp/pgtable.c
index 2cb3867eb7c2bad97ed2e9eb1695e4dcd9e233bb..cdf8e76b0be141380c95a39e76398a222be75c93 100644 (file)
--- a/arch/arm64/kvm/hyp/pgtable.c
+++ b/arch/arm64/kvm/hyp/pgtable.c
@@ -61,7 +61,7 @@ struct kvm_pgtable_walk_data {
 
 static bool kvm_phys_is_valid(u64 phys)
 {
-       return phys < BIT(id_aa64mmfr0_parange_to_phys_shift(ID_AA64MMFR0_PARANGE_MAX));
+       return phys < BIT(id_aa64mmfr0_parange_to_phys_shift(ID_AA64MMFR0_EL1_PARANGE_MAX));
 }
 
 static bool kvm_block_mapping_supported(u64 addr, u64 end, u64 phys, u32 level)

diff --git a/arch/arm64/kvm/reset.c b/arch/arm64/kvm/reset.c
index 0e08fbe68715e8e26623f086c1aedde9e8069b36..5ae18472205a9f34b73eb087b1ba383edee46ad0 100644 (file)
--- a/arch/arm64/kvm/reset.c
+++ b/arch/arm64/kvm/reset.c
@@ -359,7 +359,7 @@ int kvm_set_ipa_limit(void)
 
        mmfr0 = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
        parange = cpuid_feature_extract_unsigned_field(mmfr0,
-                               ID_AA64MMFR0_PARANGE_SHIFT);
+                               ID_AA64MMFR0_EL1_PARANGE_SHIFT);
        /*
         * IPA size beyond 48 bits could not be supported
         * on either 4K or 16K page size. Hence let's cap
@@ -367,20 +367,20 @@ int kvm_set_ipa_limit(void)
         * on the system.
         */
        if (PAGE_SIZE != SZ_64K)
-               parange = min(parange, (unsigned int)ID_AA64MMFR0_PARANGE_48);
+               parange = min(parange, (unsigned int)ID_AA64MMFR0_EL1_PARANGE_48);
 
        /*
         * Check with ARMv8.5-GTG that our PAGE_SIZE is supported at
         * Stage-2. If not, things will stop very quickly.
         */
-       switch (cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_TGRAN_2_SHIFT)) {
-       case ID_AA64MMFR0_TGRAN_2_SUPPORTED_NONE:
+       switch (cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_EL1_TGRAN_2_SHIFT)) {
+       case ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_NONE:
                kvm_err("PAGE_SIZE not supported at Stage-2, giving up\n");
                return -EINVAL;
-       case ID_AA64MMFR0_TGRAN_2_SUPPORTED_DEFAULT:
+       case ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_DEFAULT:
                kvm_debug("PAGE_SIZE supported at Stage-2 (default)\n");
                break;
-       case ID_AA64MMFR0_TGRAN_2_SUPPORTED_MIN ... ID_AA64MMFR0_TGRAN_2_SUPPORTED_MAX:
+       case ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MIN ... ID_AA64MMFR0_EL1_TGRAN_2_SUPPORTED_MAX:
                kvm_debug("PAGE_SIZE supported at Stage-2 (advertised)\n");
                break;
        default:

diff --git a/arch/arm64/mm/context.c b/arch/arm64/mm/context.c
index b8b4cf0bcf39b795c6703a90d73c2b2712cf2efd..8f38a5452d0520607b74a2a14218498d89fa78e4 100644 (file)
--- a/arch/arm64/mm/context.c
+++ b/arch/arm64/mm/context.c
@@ -43,17 +43,17 @@ static u32 get_cpu_asid_bits(void)
 {
        u32 asid;
        int fld = cpuid_feature_extract_unsigned_field(read_cpuid(ID_AA64MMFR0_EL1),
-                                               ID_AA64MMFR0_ASID_SHIFT);
+                                               ID_AA64MMFR0_EL1_ASID_SHIFT);
 
        switch (fld) {
        default:
                pr_warn("CPU%d: Unknown ASID size (%d); assuming 8-bit\n",
                                        smp_processor_id(),  fld);
                fallthrough;
-       case ID_AA64MMFR0_ASID_8:
+       case ID_AA64MMFR0_EL1_ASID_8:
                asid = 8;
                break;
-       case ID_AA64MMFR0_ASID_16:
+       case ID_AA64MMFR0_EL1_ASID_16:
                asid = 16;
        }
 

diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c
index b9af30be813eefa89d8385fc90d098175e102cd8..4b4651ee47f271a76281055a8b542e2573711611 100644 (file)
--- a/arch/arm64/mm/init.c
+++ b/arch/arm64/mm/init.c
@@ -360,7 +360,7 @@ void __init arm64_memblock_init(void)
                extern u16 memstart_offset_seed;
                u64 mmfr0 = read_cpuid(ID_AA64MMFR0_EL1);
                int parange = cpuid_feature_extract_unsigned_field(
-                                       mmfr0, ID_AA64MMFR0_PARANGE_SHIFT);
+                                       mmfr0, ID_AA64MMFR0_EL1_PARANGE_SHIFT);
                s64 range = linear_region_size -
                            BIT(id_aa64mmfr0_parange_to_phys_shift(parange));
 

diff --git a/drivers/firmware/efi/libstub/arm64-stub.c b/drivers/firmware/efi/libstub/arm64-stub.c
index 577173ee1f83d4eebca0100e2941cd47e3ae34b2..60973e84d7abe92f18b3d5d29cab30372f49646b 100644 (file)
--- a/drivers/firmware/efi/libstub/arm64-stub.c
+++ b/drivers/firmware/efi/libstub/arm64-stub.c
@@ -23,8 +23,8 @@ efi_status_t check_platform_features(void)
        if (IS_ENABLED(CONFIG_ARM64_4K_PAGES))
                return EFI_SUCCESS;
 
-       tg = (read_cpuid(ID_AA64MMFR0_EL1) >> ID_AA64MMFR0_TGRAN_SHIFT) & 0xf;
-       if (tg < ID_AA64MMFR0_TGRAN_SUPPORTED_MIN || tg > ID_AA64MMFR0_TGRAN_SUPPORTED_MAX) {
+       tg = (read_cpuid(ID_AA64MMFR0_EL1) >> ID_AA64MMFR0_EL1_TGRAN_SHIFT) & 0xf;
+       if (tg < ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MIN || tg > ID_AA64MMFR0_EL1_TGRAN_SUPPORTED_MAX) {
                if (IS_ENABLED(CONFIG_ARM64_64K_PAGES))
                        efi_err("This 64 KB granular kernel is not supported by your CPU\n");
                else

diff --git a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
index 1ef7bbb4acf30d64dc48b3bcc8131a6aec027f67..da67a75cdaad78ef8b6ec37265c3dca77a5adaae 100644 (file)
--- a/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
+++ b/drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3-sva.c
@@ -150,7 +150,7 @@ static struct arm_smmu_ctx_desc *arm_smmu_alloc_shared_cd(struct mm_struct *mm)
        }
 
        reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
-       par = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_PARANGE_SHIFT);
+       par = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_PARANGE_SHIFT);
        tcr |= FIELD_PREP(CTXDESC_CD_0_TCR_IPS, par);
 
        cd->ttbr = virt_to_phys(mm->pgd);
@@ -425,13 +425,13 @@ bool arm_smmu_sva_supported(struct arm_smmu_device *smmu)
         * addresses larger than what we support.
         */
        reg = read_sanitised_ftr_reg(SYS_ID_AA64MMFR0_EL1);
-       fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_PARANGE_SHIFT);
+       fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_PARANGE_SHIFT);
        oas = id_aa64mmfr0_parange_to_phys_shift(fld);
        if (smmu->oas < oas)
                return false;
 
        /* We can support bigger ASIDs than the CPU, but not smaller */
-       fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_ASID_SHIFT);
+       fld = cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR0_EL1_ASID_SHIFT);
        asid_bits = fld ? 16 : 8;
        if (smmu->asid_bits < asid_bits)
                return false;