cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_state

Same as for ports and dports, also store the endpoint's Component
Register mappings, use struct cxl_dev_state for that.

Keep the Component Register base address @component_reg_phys a bit to
not break functionality. It will be removed after the transition in a
later patch.

Signed-off-by: Terry Bowman <terry.bowman@amd.com>
Signed-off-by: Robert Richter <rrichter@amd.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://lore.kernel.org/r/20231018171713.1883517-7-rrichter@amd.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>

diff --git a/drivers/cxl/core/mbox.c b/drivers/cxl/core/mbox.c
index 4df4f614f490ef96d26f412a9cff42e52d246486..7e1c4d6f2e392c418b2cda4cca518390a2ea0f1d 100644 (file)
--- a/drivers/cxl/core/mbox.c
+++ b/drivers/cxl/core/mbox.c
@@ -1377,6 +1377,8 @@ struct cxl_memdev_state *cxl_memdev_state_create(struct device *dev)
        mutex_init(&mds->mbox_mutex);
        mutex_init(&mds->event.log_lock);
        mds->cxlds.dev = dev;
+       mds->cxlds.reg_map.host = dev;
+       mds->cxlds.reg_map.resource = CXL_RESOURCE_NONE;
        mds->cxlds.type = CXL_DEVTYPE_CLASSMEM;
 
        return mds;

diff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h
index 706f8a6d1ef43c78dfdebd62cd5b55347186fdbb..8fb8db47c3b7d86f121f0c0c7395604e43ae732d 100644 (file)
--- a/drivers/cxl/cxlmem.h
+++ b/drivers/cxl/cxlmem.h
@@ -397,6 +397,7 @@ enum cxl_devtype {
  *
  * @dev: The device associated with this CXL state
  * @cxlmd: The device representing the CXL.mem capabilities of @dev
+ * @reg_map: component and ras register mapping parameters
  * @regs: Parsed register blocks
  * @cxl_dvsec: Offset to the PCIe device DVSEC
  * @rcd: operating in RCD mode (CXL 3.0 9.11.8 CXL Devices Attached to an RCH)
@@ -411,6 +412,7 @@ enum cxl_devtype {
 struct cxl_dev_state {
        struct device *dev;
        struct cxl_memdev *cxlmd;
+       struct cxl_register_map reg_map;
        struct cxl_regs regs;
        int cxl_dvsec;
        bool rcd;

diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c
index f9d852957809f5c29048ce3349b485e0dc1b7f96..a6ad9bcb96b4a5f8d7fcd3b9c06220e571a6c661 100644 (file)
--- a/drivers/cxl/pci.c
+++ b/drivers/cxl/pci.c
@@ -835,15 +835,16 @@ static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id)
         * still be useful for management functions so don't return an error.
         */
        cxlds->component_reg_phys = CXL_RESOURCE_NONE;
-       rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, &map);
+       rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT,
+                               &cxlds->reg_map);
        if (rc)
                dev_warn(&pdev->dev, "No component registers (%d)\n", rc);
-       else if (!map.component_map.ras.valid)
+       else if (!cxlds->reg_map.component_map.ras.valid)
                dev_dbg(&pdev->dev, "RAS registers not found\n");
 
-       cxlds->component_reg_phys = map.resource;
+       cxlds->component_reg_phys = cxlds->reg_map.resource;
 
-       rc = cxl_map_component_regs(&map, &cxlds->regs.component,
+       rc = cxl_map_component_regs(&cxlds->reg_map, &cxlds->regs.component,
                                    BIT(CXL_CM_CAP_CAP_ID_RAS));
        if (rc)
                dev_dbg(&pdev->dev, "Failed to map RAS capability.\n");