drm/i915: Use _MMIO_TRANS2() where appropriate

Stop hand rolling _MMIO_TRANS2() and just use the real thing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220623130900.26078-7-ville.syrjala@linux.intel.com
Reviewed-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b8c254d8d6b636d92dc962ac25034c6551e6378d..3f0ad77c083a2d1fb5ba5824c57b38337a521133 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -164,10 +164,9 @@
 #define _MMIO_PIPE2(pipe, reg)         _MMIO(INTEL_INFO(dev_priv)->display.pipe_offsets[(pipe)] - \
                                              INTEL_INFO(dev_priv)->display.pipe_offsets[PIPE_A] + \
                                              DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _TRANS2(tran, reg)             (INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
-                                        INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
-                                        DISPLAY_MMIO_BASE(dev_priv) + (reg))
-#define _MMIO_TRANS2(tran, reg)                _MMIO(_TRANS2(tran, reg))
+#define _MMIO_TRANS2(tran, reg)                _MMIO(INTEL_INFO(dev_priv)->display.trans_offsets[(tran)] - \
+                                             INTEL_INFO(dev_priv)->display.trans_offsets[TRANSCODER_A] + \
+                                             DISPLAY_MMIO_BASE(dev_priv) + (reg))
 #define _MMIO_CURSOR2(pipe, reg)       _MMIO(INTEL_INFO(dev_priv)->display.cursor_offsets[(pipe)] - \
                                              INTEL_INFO(dev_priv)->display.cursor_offsets[PIPE_A] + \
                                              DISPLAY_MMIO_BASE(dev_priv) + (reg))
@@ -2147,7 +2146,7 @@
  */
 #define _SRD_CTL_A                             0x60800
 #define _SRD_CTL_EDP                           0x6f800
-#define EDP_PSR_CTL(tran)                      _MMIO(_TRANS2(tran, _SRD_CTL_A))
+#define EDP_PSR_CTL(tran)                      _MMIO_TRANS2(tran, _SRD_CTL_A)
 #define   EDP_PSR_ENABLE                       (1 << 31)
 #define   BDW_PSR_SINGLE_FRAME                 (1 << 30)
 #define   EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK  (1 << 29) /* SW can't modify */
@@ -2193,11 +2192,11 @@
 
 #define _SRD_AUX_DATA_A                                0x60814
 #define _SRD_AUX_DATA_EDP                      0x6f814
-#define EDP_PSR_AUX_DATA(tran, i)              _MMIO(_TRANS2(tran, _SRD_AUX_DATA_A) + (i) + 4) /* 5 registers */
+#define EDP_PSR_AUX_DATA(tran, i)              _MMIO_TRANS2(tran, _SRD_AUX_DATA_A + (i) + 4) /* 5 registers */
 
 #define _SRD_STATUS_A                          0x60840
 #define _SRD_STATUS_EDP                                0x6f840
-#define EDP_PSR_STATUS(tran)                   _MMIO(_TRANS2(tran, _SRD_STATUS_A))
+#define EDP_PSR_STATUS(tran)                   _MMIO_TRANS2(tran, _SRD_STATUS_A)
 #define   EDP_PSR_STATUS_STATE_MASK            (7 << 29)
 #define   EDP_PSR_STATUS_STATE_SHIFT           29
 #define   EDP_PSR_STATUS_STATE_IDLE            (0 << 29)
@@ -2224,13 +2223,13 @@
 
 #define _SRD_PERF_CNT_A                        0x60844
 #define _SRD_PERF_CNT_EDP              0x6f844
-#define EDP_PSR_PERF_CNT(tran)         _MMIO(_TRANS2(tran, _SRD_PERF_CNT_A))
+#define EDP_PSR_PERF_CNT(tran)         _MMIO_TRANS2(tran, _SRD_PERF_CNT_A)
 #define   EDP_PSR_PERF_CNT_MASK                0xffffff
 
 /* PSR_MASK on SKL+ */
 #define _SRD_DEBUG_A                           0x60860
 #define _SRD_DEBUG_EDP                         0x6f860
-#define EDP_PSR_DEBUG(tran)                    _MMIO(_TRANS2(tran, _SRD_DEBUG_A))
+#define EDP_PSR_DEBUG(tran)                    _MMIO_TRANS2(tran, _SRD_DEBUG_A)
 #define   EDP_PSR_DEBUG_MASK_MAX_SLEEP         (1 << 28)
 #define   EDP_PSR_DEBUG_MASK_LPSP              (1 << 27)
 #define   EDP_PSR_DEBUG_MASK_MEMUP             (1 << 26)
@@ -2305,7 +2304,7 @@
 
 #define _PSR2_SU_STATUS_A              0x60914
 #define _PSR2_SU_STATUS_EDP            0x6f914
-#define _PSR2_SU_STATUS(tran, index)   _MMIO(_TRANS2(tran, _PSR2_SU_STATUS_A) + (index) * 4)
+#define _PSR2_SU_STATUS(tran, index)   _MMIO_TRANS2(tran, _PSR2_SU_STATUS_A + (index) * 4)
 #define PSR2_SU_STATUS(tran, frame)    (_PSR2_SU_STATUS(tran, (frame) / 3))
 #define PSR2_SU_STATUS_SHIFT(frame)    (((frame) % 3) * 10)
 #define PSR2_SU_STATUS_MASK(frame)     (0x3ff << PSR2_SU_STATUS_SHIFT(frame))