return NULL;
}
-static void spapr_irq_init_xics(sPAPRMachineState *spapr, Error **errp)
+static void spapr_irq_init_xics(sPAPRMachineState *spapr, int nr_irqs,
+ Error **errp)
{
MachineState *machine = MACHINE(spapr);
- int nr_irqs = spapr->irq->nr_irqs;
Error *local_err = NULL;
if (kvm_enabled()) {
/*
* XIVE IRQ backend.
*/
-static void spapr_irq_init_xive(sPAPRMachineState *spapr, Error **errp)
+static void spapr_irq_init_xive(sPAPRMachineState *spapr, int nr_irqs,
+ Error **errp)
{
MachineState *machine = MACHINE(spapr);
uint32_t nr_servers = spapr_max_server_number(spapr);
}
dev = qdev_create(NULL, TYPE_SPAPR_XIVE);
- qdev_prop_set_uint32(dev, "nr-irqs", spapr->irq->nr_irqs);
+ qdev_prop_set_uint32(dev, "nr-irqs", nr_irqs);
/*
* 8 XIVE END structures per CPU. One for each available priority
*/
&spapr_irq_xive : &spapr_irq_xics;
}
-static void spapr_irq_init_dual(sPAPRMachineState *spapr, Error **errp)
+static void spapr_irq_init_dual(sPAPRMachineState *spapr, int nr_irqs,
+ Error **errp)
{
MachineState *machine = MACHINE(spapr);
Error *local_err = NULL;
return;
}
- spapr_irq_xics.init(spapr, &local_err);
+ spapr_irq_xics.init(spapr, spapr_irq_xics.nr_irqs, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
*/
spapr->ics->offset = 0;
- spapr_irq_xive.init(spapr, &local_err);
+ spapr_irq_xive.init(spapr, spapr_irq_xive.nr_irqs, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
spapr_irq_msi_init(spapr, spapr->irq->nr_msis);
}
- spapr->irq->init(spapr, errp);
+ spapr->irq->init(spapr, spapr->irq->nr_irqs, errp);
spapr->qirqs = qemu_allocate_irqs(spapr->irq->set_irq, spapr,
spapr->irq->nr_irqs);
uint32_t nr_msis;
uint8_t ov5;
- void (*init)(sPAPRMachineState *spapr, Error **errp);
+ void (*init)(sPAPRMachineState *spapr, int nr_irqs, Error **errp);
int (*claim)(sPAPRMachineState *spapr, int irq, bool lsi, Error **errp);
void (*free)(sPAPRMachineState *spapr, int irq, int num);
qemu_irq (*qirq)(sPAPRMachineState *spapr, int irq);