ARM: dts: Configure interconnect target module for dra7 aes

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Tested-by: Tero Kristo <t-kristo@ti.com>
Reviewed-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index bf8c10053b0432c0532c1c5da2f2e76ad93df535..e591add8a4ac18c87bade1bf880e5ba528ad9019 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -652,26 +652,68 @@
                        };
                };
 
-               aes1: aes@4b500000 {
-                       compatible = "ti,omap4-aes";
+               aes1_target: target-module@4b500000 {
+                       compatible = "ti,sysc-omap2", "ti,sysc";
                        ti,hwmods = "aes1";
-                       reg = <0x4b500000 0xa0>;
-                       interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
-                       dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
-                       dma-names = "tx", "rx";
-                       clocks = <&l3_iclk_div>;
+                       reg = <0x4b500080 0x4>,
+                             <0x4b500084 0x4>,
+                             <0x4b500088 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+                                        SYSC_OMAP2_AUTOIDLE)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       ti,syss-mask = <1>;
+                       /* Domains (P, C): per_pwrdm, l4sec_clkdm */
+                       clocks = <&l4sec_clkctrl DRA7_L4SEC_AES1_CLKCTRL 0>;
                        clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x4b500000 0x1000>;
+
+                       aes1: aes@0 {
+                               compatible = "ti,omap4-aes";
+                               reg = <0 0xa0>;
+                               interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&edma_xbar 111 0>, <&edma_xbar 110 0>;
+                               dma-names = "tx", "rx";
+                               clocks = <&l3_iclk_div>;
+                               clock-names = "fck";
+                       };
                };
 
-               aes2: aes@4b700000 {
-                       compatible = "ti,omap4-aes";
+               aes2_target: target-module@4b700000 {
+                       compatible = "ti,sysc-omap2", "ti,sysc";
                        ti,hwmods = "aes2";
-                       reg = <0x4b700000 0xa0>;
-                       interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
-                       dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
-                       dma-names = "tx", "rx";
-                       clocks = <&l3_iclk_div>;
+                       reg = <0x4b700080 0x4>,
+                             <0x4b700084 0x4>,
+                             <0x4b700088 0x4>;
+                       reg-names = "rev", "sysc", "syss";
+                       ti,sysc-mask = <(SYSC_OMAP2_SOFTRESET |
+                                        SYSC_OMAP2_AUTOIDLE)>;
+                       ti,sysc-sidle = <SYSC_IDLE_FORCE>,
+                                       <SYSC_IDLE_NO>,
+                                       <SYSC_IDLE_SMART>,
+                                       <SYSC_IDLE_SMART_WKUP>;
+                       ti,syss-mask = <1>;
+                       /* Domains (P, C): per_pwrdm, l4sec_clkdm */
+                       clocks = <&l4sec_clkctrl DRA7_L4SEC_AES2_CLKCTRL 0>;
                        clock-names = "fck";
+                       #address-cells = <1>;
+                       #size-cells = <1>;
+                       ranges = <0x0 0x4b700000 0x1000>;
+
+                       aes2: aes@0 {
+                               compatible = "ti,omap4-aes";
+                               reg = <0 0xa0>;
+                               interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+                               dmas = <&edma_xbar 114 0>, <&edma_xbar 113 0>;
+                               dma-names = "tx", "rx";
+                               clocks = <&l3_iclk_div>;
+                               clock-names = "fck";
+                       };
                };
 
                des: des@480a5000 {