pwm: sun4i: Consistently name driver data sun4ichip

The driver uses three different names for variables of type
sun4i_pwm_chip:

	$ git grep 'struct sun4i_pwm_chip \*' v6.8-rc1 -- drivers/pwm/pwm-sun4i.c
	v6.8-rc1:drivers/pwm/pwm-sun4i.c:static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
	v6.8-rc1:drivers/pwm/pwm-sun4i.c:static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
	v6.8-rc1:drivers/pwm/pwm-sun4i.c:static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
	v6.8-rc1:drivers/pwm/pwm-sun4i.c:       struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
	v6.8-rc1:drivers/pwm/pwm-sun4i.c:static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
	v6.8-rc1:drivers/pwm/pwm-sun4i.c:       struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
	v6.8-rc1:drivers/pwm/pwm-sun4i.c:       struct sun4i_pwm_chip *sun4ichip;
	v6.8-rc1:drivers/pwm/pwm-sun4i.c:       struct sun4i_pwm_chip *sun4ichip = platform_get_drvdata(pdev);

"chip" is usually reserved for variables of type struct pwm_chip. So
pick sun4ichip as common name which better matches the type name than
sun4i_pwm.

Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Link: https://lore.kernel.org/r/705f54a13b59fff50eaa345d8b1e0c691345b996.1707900770.git.u.kleine-koenig@pengutronix.de
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>

diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c
index c2f579043915b1f6f3b831e432603e499d66bb48..2437e5961f5ee17af89305f019bf96c5d9fb6cb4 100644 (file)
--- a/drivers/pwm/pwm-sun4i.c
+++ b/drivers/pwm/pwm-sun4i.c
@@ -95,32 +95,32 @@ static inline struct sun4i_pwm_chip *to_sun4i_pwm_chip(struct pwm_chip *chip)
        return container_of(chip, struct sun4i_pwm_chip, chip);
 }
 
-static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *chip,
+static inline u32 sun4i_pwm_readl(struct sun4i_pwm_chip *sun4ichip,
                                  unsigned long offset)
 {
-       return readl(chip->base + offset);
+       return readl(sun4ichip->base + offset);
 }
 
-static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *chip,
+static inline void sun4i_pwm_writel(struct sun4i_pwm_chip *sun4ichip,
                                    u32 val, unsigned long offset)
 {
-       writel(val, chip->base + offset);
+       writel(val, sun4ichip->base + offset);
 }
 
 static int sun4i_pwm_get_state(struct pwm_chip *chip,
                               struct pwm_device *pwm,
                               struct pwm_state *state)
 {
-       struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
+       struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip);
        u64 clk_rate, tmp;
        u32 val;
        unsigned int prescaler;
 
-       clk_rate = clk_get_rate(sun4i_pwm->clk);
+       clk_rate = clk_get_rate(sun4ichip->clk);
        if (!clk_rate)
                return -EINVAL;
 
-       val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
+       val = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);
 
        /*
         * PWM chapter in H6 manual has a diagram which explains that if bypass
@@ -128,7 +128,7 @@ static int sun4i_pwm_get_state(struct pwm_chip *chip,
         * proved that also enable bit is ignored in this case.
         */
        if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) &&
-           sun4i_pwm->data->has_direct_mod_clk_output) {
+           sun4ichip->data->has_direct_mod_clk_output) {
                state->period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, clk_rate);
                state->duty_cycle = DIV_ROUND_UP_ULL(state->period, 2);
                state->polarity = PWM_POLARITY_NORMAL;
@@ -137,7 +137,7 @@ static int sun4i_pwm_get_state(struct pwm_chip *chip,
        }
 
        if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) &&
-           sun4i_pwm->data->has_prescaler_bypass)
+           sun4ichip->data->has_prescaler_bypass)
                prescaler = 1;
        else
                prescaler = prescaler_table[PWM_REG_PRESCAL(val, pwm->hwpwm)];
@@ -156,7 +156,7 @@ static int sun4i_pwm_get_state(struct pwm_chip *chip,
        else
                state->enabled = false;
 
-       val = sun4i_pwm_readl(sun4i_pwm, PWM_CH_PRD(pwm->hwpwm));
+       val = sun4i_pwm_readl(sun4ichip, PWM_CH_PRD(pwm->hwpwm));
 
        tmp = (u64)prescaler * NSEC_PER_SEC * PWM_REG_DTY(val);
        state->duty_cycle = DIV_ROUND_CLOSEST_ULL(tmp, clk_rate);
@@ -167,7 +167,7 @@ static int sun4i_pwm_get_state(struct pwm_chip *chip,
        return 0;
 }
 
-static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
+static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4ichip,
                               const struct pwm_state *state,
                               u32 *dty, u32 *prd, unsigned int *prsclr,
                               bool *bypass)
@@ -175,9 +175,9 @@ static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
        u64 clk_rate, div = 0;
        unsigned int prescaler = 0;
 
-       clk_rate = clk_get_rate(sun4i_pwm->clk);
+       clk_rate = clk_get_rate(sun4ichip->clk);
 
-       *bypass = sun4i_pwm->data->has_direct_mod_clk_output &&
+       *bypass = sun4ichip->data->has_direct_mod_clk_output &&
                  state->enabled &&
                  (state->period * clk_rate >= NSEC_PER_SEC) &&
                  (state->period * clk_rate < 2 * NSEC_PER_SEC) &&
@@ -187,7 +187,7 @@ static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
        if (*bypass)
                return 0;
 
-       if (sun4i_pwm->data->has_prescaler_bypass) {
+       if (sun4ichip->data->has_prescaler_bypass) {
                /* First, test without any prescaler when available */
                prescaler = PWM_PRESCAL_MASK;
                /*
@@ -233,7 +233,7 @@ static int sun4i_pwm_calculate(struct sun4i_pwm_chip *sun4i_pwm,
 static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
                           const struct pwm_state *state)
 {
-       struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip);
+       struct sun4i_pwm_chip *sun4ichip = to_sun4i_pwm_chip(chip);
        struct pwm_state cstate;
        u32 ctrl, duty = 0, period = 0, val;
        int ret;
@@ -243,31 +243,31 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
        pwm_get_state(pwm, &cstate);
 
        if (!cstate.enabled) {
-               ret = clk_prepare_enable(sun4i_pwm->clk);
+               ret = clk_prepare_enable(sun4ichip->clk);
                if (ret) {
                        dev_err(pwmchip_parent(chip), "failed to enable PWM clock\n");
                        return ret;
                }
        }
 
-       ret = sun4i_pwm_calculate(sun4i_pwm, state, &duty, &period, &prescaler,
+       ret = sun4i_pwm_calculate(sun4ichip, state, &duty, &period, &prescaler,
                                  &bypass);
        if (ret) {
                dev_err(pwmchip_parent(chip), "period exceeds the maximum value\n");
                if (!cstate.enabled)
-                       clk_disable_unprepare(sun4i_pwm->clk);
+                       clk_disable_unprepare(sun4ichip->clk);
                return ret;
        }
 
-       spin_lock(&sun4i_pwm->ctrl_lock);
-       ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
+       spin_lock(&sun4ichip->ctrl_lock);
+       ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);
 
-       if (sun4i_pwm->data->has_direct_mod_clk_output) {
+       if (sun4ichip->data->has_direct_mod_clk_output) {
                if (bypass) {
                        ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm);
                        /* We can skip other parameter */
-                       sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
-                       spin_unlock(&sun4i_pwm->ctrl_lock);
+                       sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
+                       spin_unlock(&sun4ichip->ctrl_lock);
                        return 0;
                }
 
@@ -277,14 +277,14 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
        if (PWM_REG_PRESCAL(ctrl, pwm->hwpwm) != prescaler) {
                /* Prescaler changed, the clock has to be gated */
                ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
-               sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+               sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
 
                ctrl &= ~BIT_CH(PWM_PRESCAL_MASK, pwm->hwpwm);
                ctrl |= BIT_CH(prescaler, pwm->hwpwm);
        }
 
        val = (duty & PWM_DTY_MASK) | PWM_PRD(period);
-       sun4i_pwm_writel(sun4i_pwm, val, PWM_CH_PRD(pwm->hwpwm));
+       sun4i_pwm_writel(sun4ichip, val, PWM_CH_PRD(pwm->hwpwm));
 
        if (state->polarity != PWM_POLARITY_NORMAL)
                ctrl &= ~BIT_CH(PWM_ACT_STATE, pwm->hwpwm);
@@ -296,9 +296,9 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
        if (state->enabled)
                ctrl |= BIT_CH(PWM_EN, pwm->hwpwm);
 
-       sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
+       sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
 
-       spin_unlock(&sun4i_pwm->ctrl_lock);
+       spin_unlock(&sun4ichip->ctrl_lock);
 
        if (state->enabled)
                return 0;
@@ -310,14 +310,14 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
        else
                usleep_range(delay_us, delay_us * 2);
 
-       spin_lock(&sun4i_pwm->ctrl_lock);
-       ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG);
+       spin_lock(&sun4ichip->ctrl_lock);
+       ctrl = sun4i_pwm_readl(sun4ichip, PWM_CTRL_REG);
        ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm);
        ctrl &= ~BIT_CH(PWM_EN, pwm->hwpwm);
-       sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG);
-       spin_unlock(&sun4i_pwm->ctrl_lock);
+       sun4i_pwm_writel(sun4ichip, ctrl, PWM_CTRL_REG);
+       spin_unlock(&sun4ichip->ctrl_lock);
 
-       clk_disable_unprepare(sun4i_pwm->clk);
+       clk_disable_unprepare(sun4ichip->clk);
 
        return 0;
 }