clk: qcom: dispcc-sm8250: Add EDP clocks

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20210511041719.591969-2-bjorn.andersson@linaro.org
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/qcom/dispcc-sm8250.c b/drivers/clk/qcom/dispcc-sm8250.c
index 12ef6f1d5c6284fb27c70af6de1487b55b6a3a36..601c7c0ba483afa312e050324195def9e97177be 100644 (file)
--- a/drivers/clk/qcom/dispcc-sm8250.c
+++ b/drivers/clk/qcom/dispcc-sm8250.c
@@ -26,6 +26,8 @@ enum {
        P_DISP_CC_PLL1_OUT_MAIN,
        P_DP_PHY_PLL_LINK_CLK,
        P_DP_PHY_PLL_VCO_DIV_CLK,
+       P_EDP_PHY_PLL_LINK_CLK,
+       P_EDP_PHY_PLL_VCO_DIV_CLK,
        P_DSI0_PHY_PLL_OUT_BYTECLK,
        P_DSI0_PHY_PLL_OUT_DSICLK,
        P_DSI1_PHY_PLL_OUT_BYTECLK,
@@ -134,6 +136,18 @@ static const struct clk_parent_data disp_cc_parent_data_3[] = {
        { .hw = &disp_cc_pll1.clkr.hw },
 };
 
+static const struct parent_map disp_cc_parent_map_4[] = {
+       { P_BI_TCXO, 0 },
+       { P_EDP_PHY_PLL_LINK_CLK, 1 },
+       { P_EDP_PHY_PLL_VCO_DIV_CLK, 2},
+};
+
+static const struct clk_parent_data disp_cc_parent_data_4[] = {
+       { .fw_name = "bi_tcxo" },
+       { .fw_name = "edp_phy_pll_link_clk" },
+       { .fw_name = "edp_phy_pll_vco_div_clk" },
+};
+
 static const struct parent_map disp_cc_parent_map_5[] = {
        { P_BI_TCXO, 0 },
        { P_DISP_CC_PLL0_OUT_MAIN, 1 },
@@ -158,6 +172,18 @@ static const struct clk_parent_data disp_cc_parent_data_6[] = {
        { .fw_name = "dsi1_phy_pll_out_dsiclk" },
 };
 
+static const struct parent_map disp_cc_parent_map_7[] = {
+       { P_BI_TCXO, 0 },
+       { P_DISP_CC_PLL1_OUT_MAIN, 4 },
+       /* { P_DISP_CC_PLL1_OUT_EVEN, 5 }, */
+};
+
+static const struct clk_parent_data disp_cc_parent_data_7[] = {
+       { .fw_name = "bi_tcxo" },
+       { .hw = &disp_cc_pll1.clkr.hw },
+       /* { .hw = &disp_cc_pll1_out_even.clkr.hw }, */
+};
+
 static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
        F(19200000, P_BI_TCXO, 1, 0, 0),
        F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
@@ -261,7 +287,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
                .name = "disp_cc_mdss_dp_link1_clk_src",
                .parent_data = disp_cc_parent_data_0,
                .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
-               .ops = &clk_rcg2_ops,
+               .ops = &clk_byte2_ops,
        },
 };
 
@@ -275,7 +301,7 @@ static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
                .name = "disp_cc_mdss_dp_link_clk_src",
                .parent_data = disp_cc_parent_data_0,
                .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
-               .ops = &clk_rcg2_ops,
+               .ops = &clk_byte2_ops,
        },
 };
 
@@ -318,6 +344,153 @@ static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
        },
 };
 
+static struct clk_rcg2 disp_cc_mdss_edp_aux_clk_src = {
+       .cmd_rcgr = 0x228c,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_1,
+       .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_edp_aux_clk_src",
+               .parent_data = disp_cc_parent_data_1,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_edp_gtc_clk_src = {
+       .cmd_rcgr = 0x22a4,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_7,
+       .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_edp_gtc_clk_src",
+               .parent_data = disp_cc_parent_data_7,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_7),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_edp_link_clk_src = {
+       .cmd_rcgr = 0x2270,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_4,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_edp_link_clk_src",
+               .parent_data = disp_cc_parent_data_4,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_byte2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_edp_pixel_clk_src = {
+       .cmd_rcgr = 0x2258,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_4,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_edp_pixel_clk_src",
+               .parent_data = disp_cc_parent_data_4,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
+               .ops = &clk_dp_ops,
+       },
+};
+
+static struct clk_branch disp_cc_mdss_edp_aux_clk = {
+       .halt_reg = 0x2078,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x2078,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "disp_cc_mdss_edp_aux_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &disp_cc_mdss_edp_aux_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch disp_cc_mdss_edp_gtc_clk = {
+       .halt_reg = 0x207c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x207c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "disp_cc_mdss_edp_gtc_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &disp_cc_mdss_edp_gtc_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch disp_cc_mdss_edp_link_clk = {
+       .halt_reg = 0x2070,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x2070,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "disp_cc_mdss_edp_link_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &disp_cc_mdss_edp_link_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch disp_cc_mdss_edp_link_intf_clk = {
+       .halt_reg = 0x2074,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x2074,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "disp_cc_mdss_edp_link_intf_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &disp_cc_mdss_edp_link_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_GET_RATE_NOCACHE,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
+static struct clk_branch disp_cc_mdss_edp_pixel_clk = {
+       .halt_reg = 0x206c,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x206c,
+               .enable_mask = BIT(0),
+               .hw.init = &(struct clk_init_data){
+                       .name = "disp_cc_mdss_edp_pixel_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &disp_cc_mdss_edp_pixel_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
        .cmd_rcgr = 0x2148,
        .mnd_width = 0,
@@ -987,6 +1160,15 @@ static struct clk_regmap *disp_cc_sm8250_clocks[] = {
        [DISP_CC_MDSS_DP_PIXEL2_CLK_SRC] = &disp_cc_mdss_dp_pixel2_clk_src.clkr,
        [DISP_CC_MDSS_DP_PIXEL_CLK] = &disp_cc_mdss_dp_pixel_clk.clkr,
        [DISP_CC_MDSS_DP_PIXEL_CLK_SRC] = &disp_cc_mdss_dp_pixel_clk_src.clkr,
+       [DISP_CC_MDSS_EDP_AUX_CLK] = &disp_cc_mdss_edp_aux_clk.clkr,
+       [DISP_CC_MDSS_EDP_AUX_CLK_SRC] = &disp_cc_mdss_edp_aux_clk_src.clkr,
+       [DISP_CC_MDSS_EDP_GTC_CLK] = &disp_cc_mdss_edp_gtc_clk.clkr,
+       [DISP_CC_MDSS_EDP_GTC_CLK_SRC] = &disp_cc_mdss_edp_gtc_clk_src.clkr,
+       [DISP_CC_MDSS_EDP_LINK_CLK] = &disp_cc_mdss_edp_link_clk.clkr,
+       [DISP_CC_MDSS_EDP_LINK_CLK_SRC] = &disp_cc_mdss_edp_link_clk_src.clkr,
+       [DISP_CC_MDSS_EDP_LINK_INTF_CLK] = &disp_cc_mdss_edp_link_intf_clk.clkr,
+       [DISP_CC_MDSS_EDP_PIXEL_CLK] = &disp_cc_mdss_edp_pixel_clk.clkr,
+       [DISP_CC_MDSS_EDP_PIXEL_CLK_SRC] = &disp_cc_mdss_edp_pixel_clk_src.clkr,
        [DISP_CC_MDSS_ESC0_CLK] = &disp_cc_mdss_esc0_clk.clkr,
        [DISP_CC_MDSS_ESC0_CLK_SRC] = &disp_cc_mdss_esc0_clk_src.clkr,
        [DISP_CC_MDSS_ESC1_CLK] = &disp_cc_mdss_esc1_clk.clkr,

diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8250.h b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
index fdaca6ad5c85c6fcad817cfbc5ef3661ac04e78d..ce001cbbc27fb5a734a4d925e050e651b7dc6506 100644 (file)
--- a/include/dt-bindings/clock/qcom,dispcc-sm8250.h
+++ b/include/dt-bindings/clock/qcom,dispcc-sm8250.h
@@ -55,6 +55,15 @@
 #define DISP_CC_MDSS_VSYNC_CLK_SRC             45
 #define DISP_CC_PLL0                           46
 #define DISP_CC_PLL1                           47
+#define DISP_CC_MDSS_EDP_AUX_CLK               48
+#define DISP_CC_MDSS_EDP_AUX_CLK_SRC           49
+#define DISP_CC_MDSS_EDP_GTC_CLK               50
+#define DISP_CC_MDSS_EDP_GTC_CLK_SRC           51
+#define DISP_CC_MDSS_EDP_LINK_CLK              52
+#define DISP_CC_MDSS_EDP_LINK_CLK_SRC          53
+#define DISP_CC_MDSS_EDP_LINK_INTF_CLK         54
+#define DISP_CC_MDSS_EDP_PIXEL_CLK             55
+#define DISP_CC_MDSS_EDP_PIXEL_CLK_SRC         56
 
 /* DISP_CC Reset */
 #define DISP_CC_MDSS_CORE_BCR                  0