irqchip/renesas-rzg2l: Add macro to retrieve TITSR register offset based on register...

There are 2 TITSR registers available on the IA55 interrupt controller.

Add a macro that retrieves the TITSR register offset based on it's
index. This macro is useful in when adding suspend/resume support so both
TITSR registers can be accessed in a for loop.

Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Link: https://lore.kernel.org/r/20231120111820.87398-7-claudiu.beznea.uj@bp.renesas.com

diff --git a/drivers/irqchip/irq-renesas-rzg2l.c b/drivers/irqchip/irq-renesas-rzg2l.c
index d450417948e4d6ee912ddba5e501ac343df44678..34add75080e0f83107bbcc805efd234b8adeaf3a 100644 (file)
--- a/drivers/irqchip/irq-renesas-rzg2l.c
+++ b/drivers/irqchip/irq-renesas-rzg2l.c
@@ -28,8 +28,7 @@
 #define ISCR                           0x10
 #define IITSR                          0x14
 #define TSCR                           0x20
-#define TITSR0                         0x24
-#define TITSR1                         0x28
+#define TITSR(n)                       (0x24 + (n) * 4)
 #define TITSR0_MAX_INT                 16
 #define TITSEL_WIDTH                   0x2
 #define TSSR(n)                                (0x30 + ((n) * 4))
@@ -200,8 +199,7 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
        struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
        unsigned int hwirq = irqd_to_hwirq(d);
        u32 titseln = hwirq - IRQC_TINT_START;
-       u32 offset;
-       u8 sense;
+       u8 index, sense;
        u32 reg;
 
        switch (type & IRQ_TYPE_SENSE_MASK) {
@@ -217,17 +215,17 @@ static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
                return -EINVAL;
        }
 
-       offset = TITSR0;
+       index = 0;
        if (titseln >= TITSR0_MAX_INT) {
                titseln -= TITSR0_MAX_INT;
-               offset = TITSR1;
+               index = 1;
        }
 
        raw_spin_lock(&priv->lock);
-       reg = readl_relaxed(priv->base + offset);
+       reg = readl_relaxed(priv->base + TITSR(index));
        reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
        reg |= sense << (titseln * TITSEL_WIDTH);
-       writel_relaxed(reg, priv->base + offset);
+       writel_relaxed(reg, priv->base + TITSR(index));
        raw_spin_unlock(&priv->lock);
 
        return 0;