arm64: dts: qcom: sm8150: Add DISPCC node
authorKonrad Dybcio <konrad.dybcio@linaro.org>
Thu, 29 Dec 2022 10:05:09 +0000 (11:05 +0100)
committerBjorn Andersson <andersson@kernel.org>
Thu, 29 Dec 2022 16:39:43 +0000 (10:39 -0600)
Years after the SoC support has been added, it's high time for it to
get dispcc going. Add the node to ensure that.

Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Xperia 5
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229100511.979972-2-konrad.dybcio@linaro.org
arch/arm64/boot/dts/qcom/sm8150.dtsi

index 70d436dd158abac778d5cf58f738e6f5fb162574..4838091d8368a97d4d1b395e9e918df3c7553704 100644 (file)
                        qcom,bcm-voters = <&apps_bcm_voter>;
                };
 
+               dispcc: clock-controller@af00000 {
+                       compatible = "qcom,sm8150-dispcc";
+                       reg = <0 0x0af00000 0 0x10000>;
+                       clocks = <&rpmhcc RPMH_CXO_CLK>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <0>,
+                                <0>;
+                       clock-names = "bi_tcxo",
+                                     "dsi0_phy_pll_out_byteclk",
+                                     "dsi0_phy_pll_out_dsiclk",
+                                     "dsi1_phy_pll_out_byteclk",
+                                     "dsi1_phy_pll_out_dsiclk",
+                                     "dp_phy_pll_link_clk",
+                                     "dp_phy_pll_vco_div_clk";
+                       power-domains = <&rpmhpd SM8150_MMCX>;
+                       #clock-cells = <1>;
+                       #reset-cells = <1>;
+                       #power-domain-cells = <1>;
+               };
+
                pdc: interrupt-controller@b220000 {
                        compatible = "qcom,sm8150-pdc", "qcom,pdc";
                        reg = <0 0x0b220000 0 0x400>;