drm/amd/display: Use surface update inuse for pending check.

Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Acked-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
index 3e3fcf2395ae321705efe3e17bc0a377f2a707c8..8ad70625a7464f400528447e9381ba6df93b5be3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.c
@@ -821,13 +821,23 @@ bool mem_input_is_flip_pending(struct mem_input *mem_input)
 {
        uint32_t update_pending = 0;
        struct dcn10_mem_input *mi = TO_DCN10_MEM_INPUT(mem_input);
+       struct dc_plane_address earliest_inuse_address;
 
        REG_GET(DCSURF_FLIP_CONTROL,
                        SURFACE_UPDATE_PENDING, &update_pending);
 
+       REG_GET(DCSURF_SURFACE_EARLIEST_INUSE,
+                       SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part);
+
+       REG_GET(DCSURF_SURFACE_EARLIEST_INUSE_HIGH,
+                       SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part);
+
        if (update_pending)
                return true;
 
+       if (earliest_inuse_address.grph.addr.quad_part != mem_input->request_address.grph.addr.quad_part)
+               return true;
+
        mem_input->current_address = mem_input->request_address;
        return false;
 }

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
index 37683d072b421e5526a414c0405fc3f1d943bce1..9e2f1bb6995874587053f6bec96b25a892729b63 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mem_input.h
@@ -52,6 +52,14 @@
        SRI(DCSURF_PRIMARY_SURFACE_ADDRESS_C, HUBPREQ, id),\
        SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, HUBPREQ, id),\
        SRI(DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, HUBPREQ, id),\
+       SRI(DCSURF_SURFACE_INUSE, HUBPREQ, id),\
+       SRI(DCSURF_SURFACE_INUSE_HIGH, HUBPREQ, id),\
+       SRI(DCSURF_SURFACE_INUSE_C, HUBPREQ, id),\
+       SRI(DCSURF_SURFACE_INUSE_HIGH_C, HUBPREQ, id),\
+       SRI(DCSURF_SURFACE_EARLIEST_INUSE, HUBPREQ, id),\
+       SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH, HUBPREQ, id),\
+       SRI(DCSURF_SURFACE_EARLIEST_INUSE_C, HUBPREQ, id),\
+       SRI(DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, HUBPREQ, id),\
        SRI(DCSURF_SURFACE_CONTROL, HUBPREQ, id),\
        SRI(HUBPRET_CONTROL, HUBPRET, id),\
        SRI(DCN_EXPANSION_MODE, HUBPREQ, id),\
@@ -165,6 +173,14 @@ struct dcn_mi_registers {
        uint32_t DCSURF_PRIMARY_SURFACE_ADDRESS_C;
        uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C;
        uint32_t DCSURF_PRIMARY_META_SURFACE_ADDRESS_C;
+       uint32_t DCSURF_SURFACE_INUSE;
+       uint32_t DCSURF_SURFACE_INUSE_HIGH;
+       uint32_t DCSURF_SURFACE_INUSE_C;
+       uint32_t DCSURF_SURFACE_INUSE_HIGH_C;
+       uint32_t DCSURF_SURFACE_EARLIEST_INUSE;
+       uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH;
+       uint32_t DCSURF_SURFACE_EARLIEST_INUSE_C;
+       uint32_t DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C;
        uint32_t DCSURF_SURFACE_CONTROL;
        uint32_t HUBPRET_CONTROL;
        uint32_t DCN_EXPANSION_MODE;
@@ -297,6 +313,14 @@ struct dcn_mi_registers {
        MI_SF(HUBPREQ0_DCSURF_PRIMARY_SURFACE_ADDRESS_C, PRIMARY_SURFACE_ADDRESS_C, mask_sh),\
        MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_HIGH_C, PRIMARY_META_SURFACE_ADDRESS_HIGH_C, mask_sh),\
        MI_SF(HUBPREQ0_DCSURF_PRIMARY_META_SURFACE_ADDRESS_C, PRIMARY_META_SURFACE_ADDRESS_C, mask_sh),\
+       MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE, SURFACE_INUSE_ADDRESS, mask_sh),\
+       MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH, SURFACE_INUSE_ADDRESS_HIGH, mask_sh),\
+       MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_C, SURFACE_INUSE_ADDRESS_C, mask_sh),\
+       MI_SF(HUBPREQ0_DCSURF_SURFACE_INUSE_HIGH_C, SURFACE_INUSE_ADDRESS_HIGH_C, mask_sh),\
+       MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE, SURFACE_EARLIEST_INUSE_ADDRESS, mask_sh),\
+       MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, mask_sh),\
+       MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_C, SURFACE_EARLIEST_INUSE_ADDRESS_C, mask_sh),\
+       MI_SF(HUBPREQ0_DCSURF_SURFACE_EARLIEST_INUSE_HIGH_C, SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C, mask_sh),\
        MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_EN, mask_sh),\
        MI_SF(HUBPREQ0_DCSURF_SURFACE_CONTROL, PRIMARY_SURFACE_DCC_IND_64B_BLK, mask_sh),\
        MI_SF(HUBPRET0_HUBPRET_CONTROL, DET_BUF_PLANE1_BASE_ADDRESS, mask_sh),\
@@ -433,6 +457,14 @@ struct dcn_mi_registers {
        type PRIMARY_SURFACE_ADDRESS_C;\
        type PRIMARY_META_SURFACE_ADDRESS_HIGH_C;\
        type PRIMARY_META_SURFACE_ADDRESS_C;\
+       type SURFACE_INUSE_ADDRESS;\
+       type SURFACE_INUSE_ADDRESS_HIGH;\
+       type SURFACE_INUSE_ADDRESS_C;\
+       type SURFACE_INUSE_ADDRESS_HIGH_C;\
+       type SURFACE_EARLIEST_INUSE_ADDRESS;\
+       type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH;\
+       type SURFACE_EARLIEST_INUSE_ADDRESS_C;\
+       type SURFACE_EARLIEST_INUSE_ADDRESS_HIGH_C;\
        type PRIMARY_SURFACE_DCC_EN;\
        type PRIMARY_SURFACE_DCC_IND_64B_BLK;\
        type DET_BUF_PLANE1_BASE_ADDRESS;\