clk: meson: g12a: Add support for NNA CLK source clocks

This adds the Neural Network Accelerator source clocks hierarchy, it's
2 simple composite clocks to feed the AXI interface and the Core of
the Neural Network Accelerator IP.

This IP is only present on the Amlogic SM1 SoCs family.

Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200610083012.5024-3-narmstrong@baylibre.com

diff --git a/drivers/clk/meson/g12a.c b/drivers/clk/meson/g12a.c
index 30c15766ebb16bd670e686e70713749d3c8dd356..9803d44bb1578591f3a88bb246c45de7ba0d9daa 100644 (file)
--- a/drivers/clk/meson/g12a.c
+++ b/drivers/clk/meson/g12a.c
@@ -3981,6 +3981,113 @@ static struct clk_regmap g12a_spicc1_sclk = {
        },
 };
 
+/* Neural Network Accelerator source clock */
+
+static const struct clk_parent_data nna_clk_parent_data[] = {
+       { .fw_name = "xtal", },
+       { .hw = &g12a_gp0_pll.hw, },
+       { .hw = &g12a_hifi_pll.hw, },
+       { .hw = &g12a_fclk_div2p5.hw, },
+       { .hw = &g12a_fclk_div3.hw, },
+       { .hw = &g12a_fclk_div4.hw, },
+       { .hw = &g12a_fclk_div5.hw, },
+       { .hw = &g12a_fclk_div7.hw },
+};
+
+static struct clk_regmap sm1_nna_axi_clk_sel = {
+       .data = &(struct clk_regmap_mux_data){
+               .offset = HHI_NNA_CLK_CNTL,
+               .mask = 7,
+               .shift = 9,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "nna_axi_clk_sel",
+               .ops = &clk_regmap_mux_ops,
+               .parent_data = nna_clk_parent_data,
+               .num_parents = ARRAY_SIZE(nna_clk_parent_data),
+       },
+};
+
+static struct clk_regmap sm1_nna_axi_clk_div = {
+       .data = &(struct clk_regmap_div_data){
+               .offset = HHI_NNA_CLK_CNTL,
+               .shift = 0,
+               .width = 7,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "nna_axi_clk_div",
+               .ops = &clk_regmap_divider_ops,
+               .parent_hws = (const struct clk_hw *[]) {
+                       &sm1_nna_axi_clk_sel.hw
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+       },
+};
+
+static struct clk_regmap sm1_nna_axi_clk = {
+       .data = &(struct clk_regmap_gate_data){
+               .offset = HHI_NNA_CLK_CNTL,
+               .bit_idx = 8,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "nna_axi_clk",
+               .ops = &clk_regmap_gate_ops,
+               .parent_hws = (const struct clk_hw *[]) {
+                       &sm1_nna_axi_clk_div.hw
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+       },
+};
+
+static struct clk_regmap sm1_nna_core_clk_sel = {
+       .data = &(struct clk_regmap_mux_data){
+               .offset = HHI_NNA_CLK_CNTL,
+               .mask = 7,
+               .shift = 25,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "nna_core_clk_sel",
+               .ops = &clk_regmap_mux_ops,
+               .parent_data = nna_clk_parent_data,
+               .num_parents = ARRAY_SIZE(nna_clk_parent_data),
+       },
+};
+
+static struct clk_regmap sm1_nna_core_clk_div = {
+       .data = &(struct clk_regmap_div_data){
+               .offset = HHI_NNA_CLK_CNTL,
+               .shift = 16,
+               .width = 7,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "nna_core_clk_div",
+               .ops = &clk_regmap_divider_ops,
+               .parent_hws = (const struct clk_hw *[]) {
+                       &sm1_nna_core_clk_sel.hw
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+       },
+};
+
+static struct clk_regmap sm1_nna_core_clk = {
+       .data = &(struct clk_regmap_gate_data){
+               .offset = HHI_NNA_CLK_CNTL,
+               .bit_idx = 24,
+       },
+       .hw.init = &(struct clk_init_data){
+               .name = "nna_core_clk",
+               .ops = &clk_regmap_gate_ops,
+               .parent_hws = (const struct clk_hw *[]) {
+                       &sm1_nna_core_clk_div.hw
+               },
+               .num_parents = 1,
+               .flags = CLK_SET_RATE_PARENT,
+       },
+};
+
 #define MESON_GATE(_name, _reg, _bit) \
        MESON_PCLK(_name, _reg, _bit, &g12a_clk81.hw)
 
@@ -4779,6 +4886,12 @@ static struct clk_hw_onecell_data sm1_hw_onecell_data = {
                [CLKID_SPICC1_SCLK_SEL]         = &g12a_spicc1_sclk_sel.hw,
                [CLKID_SPICC1_SCLK_DIV]         = &g12a_spicc1_sclk_div.hw,
                [CLKID_SPICC1_SCLK]             = &g12a_spicc1_sclk.hw,
+               [CLKID_NNA_AXI_CLK_SEL]         = &sm1_nna_axi_clk_sel.hw,
+               [CLKID_NNA_AXI_CLK_DIV]         = &sm1_nna_axi_clk_div.hw,
+               [CLKID_NNA_AXI_CLK]             = &sm1_nna_axi_clk.hw,
+               [CLKID_NNA_CORE_CLK_SEL]        = &sm1_nna_core_clk_sel.hw,
+               [CLKID_NNA_CORE_CLK_DIV]        = &sm1_nna_core_clk_div.hw,
+               [CLKID_NNA_CORE_CLK]            = &sm1_nna_core_clk.hw,
                [NR_CLKS]                       = NULL,
        },
        .num = NR_CLKS,
@@ -5020,6 +5133,12 @@ static struct clk_regmap *const g12a_clk_regmaps[] = {
        &g12a_spicc1_sclk_sel,
        &g12a_spicc1_sclk_div,
        &g12a_spicc1_sclk,
+       &sm1_nna_axi_clk_sel,
+       &sm1_nna_axi_clk_div,
+       &sm1_nna_axi_clk,
+       &sm1_nna_core_clk_sel,
+       &sm1_nna_core_clk_div,
+       &sm1_nna_core_clk,
 };
 
 static const struct reg_sequence g12a_init_regs[] = {

diff --git a/drivers/clk/meson/g12a.h b/drivers/clk/meson/g12a.h
index a8852556836ee4ee61b69134ff3e864952857c8f..69b6a69549c77581a098ff23ac8579e402e0b711 100644 (file)
--- a/drivers/clk/meson/g12a.h
+++ b/drivers/clk/meson/g12a.h
@@ -70,6 +70,7 @@
 #define HHI_MALI_CLK_CNTL              0x1b0
 #define HHI_VPU_CLKC_CNTL              0x1b4
 #define HHI_VPU_CLK_CNTL               0x1bC
+#define HHI_NNA_CLK_CNTL               0x1C8
 #define HHI_HDMI_CLK_CNTL              0x1CC
 #define HHI_VDEC_CLK_CNTL              0x1E0
 #define HHI_VDEC2_CLK_CNTL             0x1E4
@@ -259,8 +260,12 @@
 #define CLKID_SPICC0_SCLK_DIV                  257
 #define CLKID_SPICC1_SCLK_SEL                  259
 #define CLKID_SPICC1_SCLK_DIV                  260
+#define CLKID_NNA_AXI_CLK_SEL                  262
+#define CLKID_NNA_AXI_CLK_DIV                  263
+#define CLKID_NNA_CORE_CLK_SEL                 265
+#define CLKID_NNA_CORE_CLK_DIV                 266
 
-#define NR_CLKS                                        262
+#define NR_CLKS                                        268
 
 /* include the CLKIDs that have been made part of the DT binding */
 #include <dt-bindings/clock/g12a-clkc.h>