brcmfmac: 4373 save-restore support

Use chipcommon sr_control0 register to check 4373 sr support.

Reviewed-by: Arend van Spriel <arend.vanspriel@broadcom.com>
Signed-off-by: Chi-Hsien Lin <chi-hsien.lin@cypress.com>
Signed-off-by: Kalle Valo <kvalo@codeaurora.org>

diff --git a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
index a8d3b96b727fc5e458d0805824c6cb3b21ac1e25..22534bf2a90c3d3be3a0d069ac7273664d481819 100644 (file)
--- a/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
+++ b/drivers/net/wireless/broadcom/brcm80211/brcmfmac/chip.c
@@ -1365,6 +1365,11 @@ bool brcmf_chip_sr_capable(struct brcmf_chip *pub)
                addr = CORE_CC_REG(base, sr_control1);
                reg = chip->ops->read32(chip->ctx, addr);
                return reg != 0;
+       case CY_CC_4373_CHIP_ID:
+               /* explicitly check SR engine enable bit */
+               addr = CORE_CC_REG(base, sr_control0);
+               reg = chip->ops->read32(chip->ctx, addr);
+               return (reg & CC_SR_CTL0_ENABLE_MASK) != 0;
        case CY_CC_43012_CHIP_ID:
                addr = CORE_CC_REG(pmu->base, retention_ctl);
                reg = chip->ops->read32(chip->ctx, addr);

diff --git a/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h b/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h
index e1fd499930a03a1cb0317c38de42813bea149275..de8225e6248b691253d79954b6b0342eb7658039 100644 (file)
--- a/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h
+++ b/drivers/net/wireless/broadcom/brcm80211/include/chipcommon.h
@@ -269,6 +269,25 @@ struct chipcregs {
 /* GSIO (spi/i2c) present, rev >= 37 */
 #define        CC_CAP2_GSIO            0x00000002
 
+/* sr_control0, rev >= 48 */
+#define CC_SR_CTL0_ENABLE_MASK                 BIT(0)
+#define CC_SR_CTL0_ENABLE_SHIFT                0
+#define CC_SR_CTL0_EN_SR_ENG_CLK_SHIFT 1 /* sr_clk to sr_memory enable */
+#define CC_SR_CTL0_RSRC_TRIGGER_SHIFT  2 /* Rising edge resource trigger 0 to
+                                          * sr_engine
+                                          */
+#define CC_SR_CTL0_MIN_DIV_SHIFT       6 /* Min division value for fast clk
+                                          * in sr_engine
+                                          */
+#define CC_SR_CTL0_EN_SBC_STBY_SHIFT           16
+#define CC_SR_CTL0_EN_SR_ALP_CLK_MASK_SHIFT    18
+#define CC_SR_CTL0_EN_SR_HT_CLK_SHIFT          19
+#define CC_SR_CTL0_ALLOW_PIC_SHIFT     20 /* Allow pic to separate power
+                                           * domains
+                                           */
+#define CC_SR_CTL0_MAX_SR_LQ_CLK_CNT_SHIFT     25
+#define CC_SR_CTL0_EN_MEM_DISABLE_FOR_SLEEP    30
+
 /* pmucapabilities */
 #define PCAP_REV_MASK  0x000000ff
 #define PCAP_RC_MASK   0x00001f00