clk: rockchip: fix rk3568 cpll clk gate bits
authorPeter Geis <pgwipeout@gmail.com>
Wed, 19 May 2021 17:41:49 +0000 (13:41 -0400)
committerHeiko Stuebner <heiko@sntech.de>
Sun, 23 May 2021 23:49:45 +0000 (01:49 +0200)
The cpll clk gate bits had an ordering issue. This led to the loss of
the boot sdmmc controller when the gmac was shut down with:
`ip link set eth0 down`
as the cpll_100m was shut off instead of the cpll_62p5.
cpll_62p5, cpll_50m, cpll_25m were all off by one with cpll_100m
misplaced.

Fixes: cf911d89c4c5 ("clk: rockchip: add clock controller for rk3568")
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Reviewed-by: Elaine Zhang<zhangqing@rock-chips.com>
Link: https://lore.kernel.org/r/20210519174149.3691335-1-pgwipeout@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
drivers/clk/rockchip/clk-rk3568.c

index 946ea2f45bf3b3b28b4dffa267f0392babc073a0..75ca855e720df1d026c037664dfca3543d9e330e 100644 (file)
@@ -454,17 +454,17 @@ static struct rockchip_clk_branch rk3568_clk_branches[] __initdata = {
        COMPOSITE_NOMUX(CPLL_125M, "cpll_125m", "cpll", CLK_IGNORE_UNUSED,
                        RK3568_CLKSEL_CON(80), 0, 5, DFLAGS,
                        RK3568_CLKGATE_CON(35), 10, GFLAGS),
+       COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
+                       RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
+                       RK3568_CLKGATE_CON(35), 11, GFLAGS),
        COMPOSITE_NOMUX(CPLL_62P5M, "cpll_62p5", "cpll", CLK_IGNORE_UNUSED,
                        RK3568_CLKSEL_CON(80), 8, 5, DFLAGS,
-                       RK3568_CLKGATE_CON(35), 11, GFLAGS),
+                       RK3568_CLKGATE_CON(35), 12, GFLAGS),
        COMPOSITE_NOMUX(CPLL_50M, "cpll_50m", "cpll", CLK_IGNORE_UNUSED,
                        RK3568_CLKSEL_CON(81), 0, 5, DFLAGS,
-                       RK3568_CLKGATE_CON(35), 12, GFLAGS),
+                       RK3568_CLKGATE_CON(35), 13, GFLAGS),
        COMPOSITE_NOMUX(CPLL_25M, "cpll_25m", "cpll", CLK_IGNORE_UNUSED,
                        RK3568_CLKSEL_CON(81), 8, 6, DFLAGS,
-                       RK3568_CLKGATE_CON(35), 13, GFLAGS),
-       COMPOSITE_NOMUX(CPLL_100M, "cpll_100m", "cpll", CLK_IGNORE_UNUSED,
-                       RK3568_CLKSEL_CON(82), 0, 5, DFLAGS,
                        RK3568_CLKGATE_CON(35), 14, GFLAGS),
        COMPOSITE_NOMUX(0, "clk_osc0_div_750k", "xin24m", CLK_IGNORE_UNUSED,
                        RK3568_CLKSEL_CON(82), 8, 6, DFLAGS,