Make SYNCI_Step and CCRes CPU-specific.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2651 c046a42c-6fe2-441c-8c8c-71466251a162

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 96ae2cd6768eb1aa4b62f4090c7c6f6371c1d9e2..75221c9c81851cb9665d0965d10d861ba4de036c 100644 (file)
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -5435,9 +5435,6 @@ void cpu_reset (CPUMIPSState *env)
     env->hflags |= MIPS_HFLAG_UM;
     env->user_mode_only = 1;
 #endif
-    /* XXX some guesswork here, values are CPU specific */
-    env->SYNCI_Step = 16;
-    env->CCRes = 2;
 }
 
 #include "translate_init.c"

diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index 456a6cd8320698e7688dff27fd80b14f7ae9f61e..f2966ea89581a77cc33e2a3fe6e354d271987658 100644 (file)
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -67,6 +67,8 @@ struct mips_def_t {
     int32_t CP0_Config3;
     int32_t CP0_Config6;
     int32_t CP0_Config7;
+    int32_t SYNCI_Step;
+    int32_t CCRes;
     int32_t CP1_fcr0;
 };
 
@@ -82,6 +84,8 @@ static mips_def_t mips_defs[] =
         .CP0_Config1 = MIPS_CONFIG1,
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
     {
@@ -91,6 +95,8 @@ static mips_def_t mips_defs[] =
         .CP0_Config1 = MIPS_CONFIG1,
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
     {
@@ -100,6 +106,8 @@ static mips_def_t mips_defs[] =
         .CP0_Config1 = MIPS_CONFIG1,
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
     {
@@ -109,6 +117,8 @@ static mips_def_t mips_defs[] =
         .CP0_Config1 = MIPS_CONFIG1,
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
     {
@@ -118,6 +128,8 @@ static mips_def_t mips_defs[] =
         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 32,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
 #else
@@ -128,6 +140,8 @@ static mips_def_t mips_defs[] =
         .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP),
         .CP0_Config2 = MIPS_CONFIG2,
         .CP0_Config3 = MIPS_CONFIG3,
+        .SYNCI_Step = 16,
+        .CCRes = 2,
         .CP1_fcr0 = MIPS_FCR0,
     },
 #endif
@@ -175,6 +189,8 @@ int cpu_mips_register (CPUMIPSState *env, mips_def_t *def)
     env->CP0_Config3 = def->CP0_Config3;
     env->CP0_Config6 = def->CP0_Config6;
     env->CP0_Config7 = def->CP0_Config7;
+    env->SYNCI_Step = def->SYNCI_Step;
+    env->CCRes = def->CCRes;
     env->fcr0 = def->CP1_fcr0;
     return 0;
 }