PCI: designware-ep: Add the doorbell mode of MSI-X in EP mode

Add the doorbell mode of MSI-X in DWC EP driver.

Link: https://lore.kernel.org/r/20200918080024.13639-3-Zhiqiang.Hou@nxp.com
Signed-off-by: Xiaowei Bao <xiaowei.bao@nxp.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>

diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c
index 500d4ca04947ced74fa83404dd97abf96a4bf9f3..5ae87e8ffb855fc53c360004cd9f7f388dceef35 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-ep.c
+++ b/drivers/pci/controller/dwc/pcie-designware-ep.c
@@ -473,6 +473,25 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
        return 0;
 }
 
+int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
+                                      u16 interrupt_num)
+{
+       struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
+       struct dw_pcie_ep_func *ep_func;
+       u32 msg_data;
+
+       ep_func = dw_pcie_ep_get_func_from_ep(ep, func_no);
+       if (!ep_func || !ep_func->msix_cap)
+               return -EINVAL;
+
+       msg_data = (func_no << PCIE_MSIX_DOORBELL_PF_SHIFT) |
+                  (interrupt_num - 1);
+
+       dw_pcie_writel_dbi(pci, PCIE_MSIX_DOORBELL, msg_data);
+
+       return 0;
+}
+
 int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
                              u16 interrupt_num)
 {

diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h
index 32102ebc5c379bb64e1b4e82744b3ea7ed592163..4b75b798de98c407b898eee272e346ee9803279f 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware.h
+++ b/drivers/pci/controller/dwc/pcie-designware.h
@@ -105,6 +105,9 @@
 #define PCIE_MISC_CONTROL_1_OFF                0x8BC
 #define PCIE_DBI_RO_WR_EN              BIT(0)
 
+#define PCIE_MSIX_DOORBELL             0x948
+#define PCIE_MSIX_DOORBELL_PF_SHIFT    24
+
 #define PCIE_PL_CHK_REG_CONTROL_STATUS                 0xB20
 #define PCIE_PL_CHK_REG_CHK_REG_START                  BIT(0)
 #define PCIE_PL_CHK_REG_CHK_REG_CONTINUOUS             BIT(1)
@@ -414,6 +417,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no,
                             u8 interrupt_num);
 int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
                             u16 interrupt_num);
+int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep, u8 func_no,
+                                      u16 interrupt_num);
 void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar);
 #else
 static inline void dw_pcie_ep_linkup(struct dw_pcie_ep *ep)
@@ -455,6 +460,13 @@ static inline int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no,
        return 0;
 }
 
+static inline int dw_pcie_ep_raise_msix_irq_doorbell(struct dw_pcie_ep *ep,
+                                                    u8 func_no,
+                                                    u16 interrupt_num)
+{
+       return 0;
+}
+
 static inline void dw_pcie_ep_reset_bar(struct dw_pcie *pci, enum pci_barno bar)
 {
 }