KVM: arm64: nv: Reset VCPU to EL2 registers if VCPU nested virt is set
authorChristoffer Dall <christoffer.dall@arm.com>
Thu, 9 Feb 2023 17:58:06 +0000 (17:58 +0000)
committerOliver Upton <oliver.upton@linux.dev>
Sat, 11 Feb 2023 09:16:11 +0000 (09:16 +0000)
Reset the VCPU with PSTATE.M = EL2h when the nested virtualization
feature is enabled on the VCPU.

Reviewed-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
Reviewed-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@arm.com>
[maz: rework register reset not to use empty data structures]
Signed-off-by: Marc Zyngier <maz@kernel.org>
Link: https://lore.kernel.org/r/20230209175820.1939006-5-maz@kernel.org
Signed-off-by: Oliver Upton <oliver.upton@linux.dev>
arch/arm64/kvm/reset.c

index e0267f672b8abec1e72bdf80c7d1abb37518ad33..d061dcc215782a15a62248fa5919dd009b8dde4b 100644 (file)
@@ -27,6 +27,7 @@
 #include <asm/kvm_asm.h>
 #include <asm/kvm_emulate.h>
 #include <asm/kvm_mmu.h>
+#include <asm/kvm_nested.h>
 #include <asm/virt.h>
 
 /* Maximum phys_shift supported for any VM on this host */
@@ -38,6 +39,9 @@ static u32 kvm_ipa_limit;
 #define VCPU_RESET_PSTATE_EL1  (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT | \
                                 PSR_F_BIT | PSR_D_BIT)
 
+#define VCPU_RESET_PSTATE_EL2  (PSR_MODE_EL2h | PSR_A_BIT | PSR_I_BIT | \
+                                PSR_F_BIT | PSR_D_BIT)
+
 #define VCPU_RESET_PSTATE_SVC  (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT | \
                                 PSR_AA32_I_BIT | PSR_AA32_F_BIT)
 
@@ -220,6 +224,10 @@ static int kvm_set_vm_width(struct kvm_vcpu *vcpu)
        if (kvm_has_mte(kvm) && is32bit)
                return -EINVAL;
 
+       /* NV is incompatible with AArch32 */
+       if (vcpu_has_nv(vcpu) && is32bit)
+               return -EINVAL;
+
        if (is32bit)
                set_bit(KVM_ARCH_FLAG_EL1_32BIT, &kvm->arch.flags);
 
@@ -272,6 +280,12 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
        if (loaded)
                kvm_arch_vcpu_put(vcpu);
 
+       /* Disallow NV+SVE for the time being */
+       if (vcpu_has_nv(vcpu) && vcpu_has_feature(vcpu, KVM_ARM_VCPU_SVE)) {
+               ret = -EINVAL;
+               goto out;
+       }
+
        if (!kvm_arm_vcpu_sve_finalized(vcpu)) {
                if (test_bit(KVM_ARM_VCPU_SVE, vcpu->arch.features)) {
                        ret = kvm_vcpu_enable_sve(vcpu);
@@ -294,6 +308,8 @@ int kvm_reset_vcpu(struct kvm_vcpu *vcpu)
        default:
                if (vcpu_el1_is_32bit(vcpu)) {
                        pstate = VCPU_RESET_PSTATE_SVC;
+               } else if (vcpu_has_nv(vcpu)) {
+                       pstate = VCPU_RESET_PSTATE_EL2;
                } else {
                        pstate = VCPU_RESET_PSTATE_EL1;
                }