drm/amdgpu/gfx11: fix me field handling in map_queue packet

Select the correct microengine (me) when using the
map_queue packet.  There are different me's for GFX,
compute, and scheduling.

Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 7614f38ff38197c92b2bf746b438d1dffcb15ac5..8a1bec70c7193267b8d513a3de1b2373caea13fd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -145,16 +145,19 @@ static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 {
        uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
        uint64_t wptr_addr = ring->wptr_gpu_addr;
-       uint32_t eng_sel = 0;
+       uint32_t me = 0, eng_sel = 0;
 
        switch (ring->funcs->type) {
        case AMDGPU_RING_TYPE_COMPUTE:
+               me = 1;
                eng_sel = 0;
                break;
        case AMDGPU_RING_TYPE_GFX:
+               me = 0;
                eng_sel = 4;
                break;
        case AMDGPU_RING_TYPE_MES:
+               me = 2;
                eng_sel = 5;
                break;
        default:
@@ -168,7 +171,7 @@ static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring,
                          PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
                          PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
                          PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
-                         PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
+                         PACKET3_MAP_QUEUES_ME((me)) |
                          PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
                          PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
                          PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |