arm64: zynqmp: Add L2 cache nodes

Describe SoC L2 cache hierarchy.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/130e5a6acbee94809b63a61cde5450fbff88cc9c.1685964230.git.michal.simek@amd.com

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index 02cfcc7169368a9000735e947e28f5542316822d..394db49ac6cbd53d4e7d85854c6a8ee95060c9bf 100644 (file)
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -33,6 +33,7 @@
                        operating-points-v2 = <&cpu_opp_table>;
                        reg = <0x0>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
                };
 
                cpu1: cpu@1 {
@@ -42,6 +43,7 @@
                        reg = <0x1>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
                };
 
                cpu2: cpu@2 {
@@ -51,6 +53,7 @@
                        reg = <0x2>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
                };
 
                cpu3: cpu@3 {
@@ -60,6 +63,13 @@
                        reg = <0x3>;
                        operating-points-v2 = <&cpu_opp_table>;
                        cpu-idle-states = <&CPU_SLEEP_0>;
+                       next-level-cache = <&L2>;
+               };
+
+               L2: l2-cache {
+                       compatible = "cache";
+                       cache-level = <2>;
+                       cache-unified;
                };
 
                idle-states {