serial: mvebu-uart: add TX interrupt trigger for pulse interrupts

Pulse interrupts (extended UART only) needs a change of state to trigger
the TX interrupt. In addition to enabling the TX_READY_INT_EN flag,
produce a FIFO state change from 'empty' to 'not full'. For this, write
only one data byte in TX start, making the TX FIFO not empty, and wait
for the TX interrupt to continue the transfer.

Signed-off-by: Allen Yan <yanwei@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@free-electrons.com>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

diff --git a/drivers/tty/serial/mvebu-uart.c b/drivers/tty/serial/mvebu-uart.c
index 6bd0c40008bb87dc394bb32ca40c48296170a3e1..e52248ec26895f9c72e363e5e80069a2d00f6026 100644 (file)
--- a/drivers/tty/serial/mvebu-uart.c
+++ b/drivers/tty/serial/mvebu-uart.c
@@ -165,8 +165,16 @@ static void mvebu_uart_stop_tx(struct uart_port *port)
 
 static void mvebu_uart_start_tx(struct uart_port *port)
 {
-       unsigned int ctl = readl(port->membase + UART_INTR(port));
+       unsigned int ctl;
+       struct circ_buf *xmit = &port->state->xmit;
 
+       if (IS_EXTENDED(port) && !uart_circ_empty(xmit)) {
+               writel(xmit->buf[xmit->tail], port->membase + UART_TSH(port));
+               xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
+               port->icount.tx++;
+       }
+
+       ctl = readl(port->membase + UART_INTR(port));
        ctl |= CTRL_TX_RDY_INT(port);
        writel(ctl, port->membase + UART_INTR(port));
 }