drm/amdgpu: force pa_sc_tile_steering_override to 0 for gfx10.3
authorHawking Zhang <Hawking.Zhang@amd.com>
Thu, 16 Jan 2020 03:07:20 +0000 (11:07 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 1 Jul 2020 05:59:09 +0000 (01:59 -0400)
pa_sc_tile_steering_override is only programmable for
gfx10.0/10.1/10.2

Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

index 750f2ff9ed9fd062499b21f90ddd109a309f57b4..66d7ae45676800e1dd5156d336f35e30252a82af 100644 (file)
@@ -95,7 +95,6 @@
 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK   0x00000FFCL
 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT 0x2
 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK   0x00000FFCL
-#define PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_Sienna_Cichlid_MASK    0x00300000L
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                      0x1580
 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX     0
 
@@ -4468,6 +4467,11 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
        uint32_t num_packer_per_sc;
        uint32_t pa_sc_tile_steering_override;
 
+       /* for ASICs that integrates GFX v10.3
+        * pa_sc_tile_steering_override should be set to 0 */
+       if (adev->asic_type == CHIP_SIENNA_CICHLID)
+               return 0;
+
        /* init num_sc */
        num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
                        adev->gfx.config.num_sc_per_sh;
@@ -4485,18 +4489,9 @@ static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *ade
        pa_sc_tile_steering_override |=
                (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
                PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
-       switch (adev->asic_type) {
-       case CHIP_SIENNA_CICHLID:
-               pa_sc_tile_steering_override |=
-                       (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
-                       PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_Sienna_Cichlid_MASK;
-               break;
-       default:
-               pa_sc_tile_steering_override |=
-                       (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
-                       PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
-               break;
-       }
+       pa_sc_tile_steering_override |=
+               (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
+               PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
 
        return pa_sc_tile_steering_override;
 }