clk: imx: imxrt1050: fix IMXRT1050_CLK_LCDIF_APB offsets
authorGiulio Benetti <giulio.benetti@benettiengineering.com>
Thu, 17 Nov 2022 18:10:11 +0000 (19:10 +0100)
committerAbel Vesa <abel.vesa@linaro.org>
Mon, 21 Nov 2022 22:04:49 +0000 (00:04 +0200)
Fix IMXRT1050_CLK_LCDIF_APB offsets.

Fixes: 7154b046d8f3 ("clk: imx: Add initial support for i.MXRT1050 clock driver")
Cc: Jesse Taube <mr.bossman075@gmail.com>
Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20221117181014.851505-1-giulio.benetti@benettiengineering.com
drivers/clk/imx/clk-imxrt1050.c

index 9539d35588ee938fa5642a073a71c2ff75ed99dc..26108e9f7e67ad5dad6501a94fb4bf65c7431fc9 100644 (file)
@@ -140,7 +140,7 @@ static int imxrt1050_clocks_probe(struct platform_device *pdev)
        hws[IMXRT1050_CLK_USDHC1] = imx_clk_hw_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2);
        hws[IMXRT1050_CLK_USDHC2] = imx_clk_hw_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4);
        hws[IMXRT1050_CLK_LPUART1] = imx_clk_hw_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24);
-       hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x74, 10);
+       hws[IMXRT1050_CLK_LCDIF_APB] = imx_clk_hw_gate2("lcdif", "lcdif_podf", ccm_base + 0x70, 28);
        hws[IMXRT1050_CLK_DMA] = imx_clk_hw_gate("dma", "ipg", ccm_base + 0x7C, 6);
        hws[IMXRT1050_CLK_DMA_MUX] = imx_clk_hw_gate("dmamux0", "ipg", ccm_base + 0x7C, 7);
        imx_check_clk_hws(hws, IMXRT1050_CLK_END);